FMC-HDMI-CAM + PYTHON-1300-C
Frame Buffer Design Tutorial
v2015_4
23 February 2016
Page
20
of
23
VITA CRC - Asserting Reset
VITA ISERDES - Releasing Reset
VITA DECODER - Releasing Reset
VITA CRC - Releasing Reset
VITA ISERDES - Status = 0x61610100
VITA ISERDES - Status = 0x61610100
VITA ISERDES - Waiting for CLK_RDY to assert
VITA ISERDES - Status = 0x61610100
VITA ISERDES - Align Start
VITA ISERDES - Waiting for ALIGN_BUSY to assert
VITA ISERDES - Status = 0x61610304
VITA ISERDES - Waiting for ALIGN_BUSY to de-assert
VITA ISERDES - Status = 0x61610100
VITA ISERDES - Status = 0x61610100
VITA ISERDES - Enabling FIFO enable
VITA DECODER - Enabling Sync Channel Decoder
VITA DECODER - Control = 0x00000002
VITA CRC - Status = 0x0000000F
VITA CRC - Status = 0x0000000F
VITA CRC - Status = 0x0000000F
VITA CRC - Status = 0x0000000F
VITA CRC - Status = 0x0000000F
VITA CRC - Status = 0x0000000F
VITA CRC - Status = 0x0000000F
VITA CRC - Status = 0x0000000F
VITA CRC - Status = 0x0000000F
VITA CRC - Status = 0x0000000F
VITA SPI Sequence 6 - Enable Sequencer
VITA_SPI[0x00C0] => 0x0800
0x0001
VITA_SPI[0x00C0] <= 0x0801
VITA SPI Sequence CDS
VITA_SPI[0x00C0] <= 0x0800
VITA_SPI[0x00CC] <= 0x01E3
VITA_SPI[0x0041] <= 0x288B
VITA_SPI[0x0029] <= 0x085F
VITA_SPI[0x002A] <= 0x4113
VITA_SPI[0x002B] <= 0x0008
VITA_SPI[0x0048] <= 0x0017
VITA_SPI[0x0180] <= 0xC800
VITA_SPI[0x0181] <= 0xFB1F
VITA_SPI[0x0182] <= 0xFB1F
VITA_SPI[0x0183] <= 0xFB12
VITA_SPI[0x0184] <= 0xF903
VITA_SPI[0x0185] <= 0xF802
VITA_SPI[0x0186] <= 0xF30F
VITA_SPI[0x0187] <= 0xF30F
VITA_SPI[0x0188] <= 0xF30F
VITA_SPI[0x0189] <= 0xF30A
VITA_SPI[0x018A] <= 0xF101
VITA_SPI[0x018B] <= 0xF00A
VITA_SPI[0x018C] <= 0xF24B
VITA_SPI[0x018D] <= 0xF226
VITA_SPI[0x018E] <= 0xF001
VITA_SPI[0x018F] <= 0xF402