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AL460A-7&13-EVB-A0-User Manual

©2009~2010 Copyright by AverLogic Technologies, Corp. Version 1.0

2

Amendments

Revise Date

Contents Author

2010.08.13

Formal Release Version 1.0

Ray Pan

Disclaimer

THE CONTENTS OF THIS DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE. AVERLOGIC
TECHNOLOGIES RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. AVERLOGIC DOES NOT
ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR
CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS. CUSTOMERS ARE ADVISED TO CONSULT WITH
AVERLOGIC OR ITS COMMERCIAL DISTRIBUTORS BEFORE ORDERING.

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Содержание AL460A-13-EVB-A0

Страница 1: ... B E A C C U R A T E A N D R E L I AB L E H O W E V E R N O R E S P O N S I B I L I T Y I S A S S U M E D B Y A V E R L O G I C F O R I T S U S E N O R F O R A N Y I N F R I N G E M E N T S O F P A T E N T S O R O T H E R R I G H T S O F T H I R D P A R T I E S T H A T M A Y R E S U L T F R O M I T S U S E N O L I C E N S E I S G R A N T E D B Y I M P L I C A T I O N O R O T H E R W I S E U N D E ...

Страница 2: ... NOTICE AVERLOGIC TECHNOLOGIES RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN AVERLOGIC DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS CUSTOMERS ARE ADVISED TO CONSULT WITH AVE...

Страница 3: ...erLogic Technologies Corp Version 1 0 3 Table of Contents 1 INTRODUCTION 4 2 ADAPTOR INTERFACE 5 2 1 ALTERA CYCLONE III INTERFACE HSMC CONNECTOR 5 2 2 AL460 EVALUATION BOARD INTERFACE 50 PIN HEADERS 7 2 3 USER CONTROL INTERFACE 8 3 ATTACHING THE AL460 EVB 9 ...

Страница 4: ...or for the FGPA board and two 50 pin female headers for the AL460 module board DST 0106A MDL A0 A1 The HSMC connector is a modified version of a standard high speed Samtec connector which is pin to pin compatible with the Cyclone III FPGA host board s HSMC connector The 50 pin female headers match the two male headers on the AL460 module DST 0106A MDL A0 A1 1 1 Hardware Description Side 1 HSMC Con...

Страница 5: ...al 41 OE HSMC_D1 Bidirectional 42 REN HSMC_D2 Bidirectional 43 DO 0 HSMC_D3 Bidirectional 44 DO 1 HSMC_D4 Bidirectional 47 DO 2 HSMC_D5 Bidirectional 48 DO 3 HSMC_D6 Bidirectional 49 DO 4 HSMC_D7 Bidirectional 50 DO 5 HSMC_D8 Bidirectional 53 DO 6 HSMC_D9 Bidirectional 54 DO 7 HSMC_D10 Bidirectional 55 DO 8 HSMC_D11 Bidirectional 56 DO 9 HSMC_D12 Bidirectional 59 DO 10 HSMC_D13 Bidirectional 60 DO...

Страница 6: ...5 DI 24 HSMC_RX_n10 Bidirectional 116 DI 23 HSMC_TX_p11 Bidirectional 119 DI 22 HSMC_RX_p11 Bidirectional 120 DI 21 HSMC_TX_n11 Bidirectional 121 DI 20 HSMC_RX_n11 Bidirectional 122 DI 19 HSMC_TX_p12 Bidirectional 125 DI 18 HSMC_RX_p12 Bidirectional 126 DI 17 HSMC_TX_n12 Bidirectional 127 DI 16 HSMC_RX_n12 Bidirectional 128 DI 15 HSMC_TX_p13 Bidirectional 131 DI 14 HSMC_RX_p13 Bidirectional 132 DI...

Страница 7: ...102 102 104 104 106 106 108 108 110 110 112 112 114 114 116 116 118 118 120 120 122 122 124 124 126 126 128 128 130 130 132 132 134 134 136 136 138 138 140 140 142 142 144 144 146 146 148 148 150 150 152 152 154 154 156 156 158 158 160 160 161 161 162 162 163 163 164 164 165 165 166 166 167 167 168 168 169 169 170 170 171 171 172 172 DO 4 DI 5 DO 6 RD_FRAME_SEL DO 5 DO 7 DO 8 RCLKO_EN RCLK DO 9 MA...

Страница 8: ...3 PLRTY is active low VD33 Jumper 1 2 PLRTY is active high GND Control signals include WEN REN WRST RRST IE OE total of 6 signals Note During memory operations the pin must be permanently connected to VD33 or GND If PLRTY level is changed during a memory operation memory data is not guaranteed TWO_FRAME_EN I Set Two Frame Mode by jumpering pins 1 2 3 on JP3 Jumper 1 2 0 Standard FIFO Mode Jumper 3...

Страница 9: ...B AL460FSB1 D0 AL460A Module DST 0106A MDL A0 A1 JP1 JP2 JP2 JP1 Diagram AL460A 7 PBF AL460A 7 PBF 50 Pins Output Header 50 Pins Input Header AVERLOGIC AVERLOGIC DO 15 0 Read Controls RCLK DO 31 16 DI 15 0 Write Controls WCLK DI 31 16 JP1 JP2 Figure AL460 Module Diagram i e the JP1 connector on the Adaptor attaches to the JP2 connector on the EVB The JP2 connector on the Adaptor attaches to the JP...

Страница 10: ...AL460A 7 13 EVB A0 User Manual 2009 2010 Copyright by AverLogic Technologies Corp Version 1 0 10 CONTACT INFORMATION Averlogic Technologies Corp E mail sales averlogic com URL http www averlogic com ...

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