Atmel XMEGA B, Руководство пользователя

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82 XMEGA B [DATASHEET]
8291B–AVR–01/2013
7.6 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-
selectable multiplication factor of from 1 to 31. The output frequency, f
OUT
, is given by the input frequency, f
IN
, multiplied
by the multiplication factor, PLL_FAC.
Four different clock sources can be chosen as input to the PLL:

2MHz internal oscillator

32MHz internal oscillator divided by 4

0.4MHz - 16MHz crystal oscillator

External clock
To enable the PLL, the following procedure must be followed:
1. Enable reference clock source.
2. Set the multiplication factor and select the clock reference for the PLL.
3. Wait until the clock reference source is stable.
4. Enable the PLL.
Hardware ensures that the PLL configuration cannot be changed when the PLL is in use. The PLL must be disabled
before a new configuration can be written.
It is not possible to use the PLL before the selected clock source is stable and the PLL has locked.
The reference clock source cannot be disabled while the PLL is running.
7.7 DFLL 2MHz and DFLL 32MHz
Two built-in digital frequency locked loops (DFLLs) can be used to improve the accuracy of the 2MHz and 32MHz
internal oscillators. The DFLL compares the oscillator frequency with a more accurate reference clock to do automatic
run-time calibration of the oscillator and compensate for temperature and voltage drift. The choices for the reference
clock sources are:

32.768kHz calibrated internal oscillator

32.768kHz crystal oscillator connected to the TOSC pins

External clock

USB start of frame
The DFLLs divide the oscillator reference clock by 32 to use a 1.024kHz reference. The reference clock is individually
selected for each DFLL, as shown on
Figure 7-6 on page 83 .
f
OUT
f
IN
PLL_FAC

=