Atmel STK511, Руководство пользователя

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STK511 Receiver Interface Board
4-4 STK511 User Guide
4842B–AVR–10/09
The following table shows how the signals from the receiver connectors (U2) are routed to the microcon-
troller I/O ports. As shipped, the STK511 Receiver Interface Board routes the Receiver Application
Board signals, necessary for stand-alone operation, to the on-board microcontroller. The remaining sig-
nals are routed to the STK500 through the expansion connectors. See section
“Receive Signal Routing”
on page 4-6 for additional information.
4.2.2 Configuration Register DIP Switches
Upon receiving power, the receiver’s OPMODE and LIMIT registers contain default settings. Any values
other than the default require programming. The OPMODE register controls Baud Rate range, Bit Check
quantity, Modulation type, Sleep polling time, and Noise Suppression. The LIMIT register controls the
maximum and minimum valid time between edges. See the receiver datasheet for more information on
the registers.
The DIP switches on the STK511 Receiver Interface Board allow individual bits in these registers to be
modified. As an added convenience, the STK511 Receiver Interface Board contains a silkscreen legend
that specifies each bit function for both registers as well as their corresponding default value.
The configuration register DIP switches connect to the following I/O ports of the ATmega8515 AVR
microcontroller which is integral to the STK511 Receiver Interface Board. The bits not listed in the table
below are set to constants in the firmware.
Receiver Signal to I/O Port Mapping
U2 Connector Receiver Application Board
Microcontroller I/O
Port Pin # ATA5743 ATA5760/1 ATA5744
12 VCC VCC VCC ---
11 GND GND GND ---
10 DATA DATA DATA PB4
9 --- --- --- ---
8 --- --- BR0 PB1
7 MODE V DIV BR1 PB3
6 D_CLK D_CLK RSSI PB2
5 SENS SENS --- ---
4 IC_Active IC_ACTIVE --- PB1
3 POL/ON POL/ON ENABLE PB0
2 --- --- --- ---
1 --- --- --- ---
Table 4-1. DIP Switch to I/O Port Mapping
OPMODE Register
Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15
--- --- PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 ---
LIMIT Register
Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15
--- --- PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC4 PC5 PC6 PC7 ---