Evaluation Kit Hardware
4-12
SAM3U-EK Development Board User Guide
6478B–ATARM–05-Oct-09
The SAM3U4E programmable clock output is used to generate the WM8731 master clock (MCLK). The
SAM3U4E ODT (On-Die Termination) feature guarantees a signal integrity on this clock line without the
need for external discrete components.
WM8731 pin 21 MODE is pulled down by default; this configures the device as a TWI device for internal
register access.
Pin15 CSB is pulled up, which sets its TWI address as 33 [0x0011011].
The WM8731 digital interface works in slave mode on the SAM3U4E Synchronous Serial Controller
(SSC) interface, which means that Codec digital audio bit clock and ADC/DAC left/right control clock are
to be generated by the SAM3U4E.
Figure 4-14.
Codec Slave Mode
The WM8731 ADC and DAC have separated left/right control clocks to run at different rates.
The bit clock is shared; it can be the SSC transmitter clock (TK) or the receiver clock (RK). The default
setting on SAM3U-EK is TK and RK shorted together through R97/R99. Please note that trying different
ADC/DAC rates would mean different RK/TK rates; this default setting can be modified.
The 0-Ohm resistors R46/R47/R97/R99 have been implemented to offer a disconnection possibility
(freeing these dedicated PIO lines for other custom usage).
BCLK
ADCLRC
DACLRC
ADCDAT
DACDAT
WM
8
7
3
1
CODEC
S
AM
3
U4E
Note: The ADC
a
nd DAC c
a
n r
u
n
a
t different r
a
te
s
BCLK
PA
3
1
PA
3
0
PA27
PA26
