Evaluation Kit Hardware
4-6
SAM3S-EK Development Board User Guide
11031A–ATARM–14-Dec-09
Figure 4-6.
USART
4.3.7.2
RS485
As noticed above, the USART1 is shared with the RS485 port, connected to the transceiver MN4, con-
nected to the 3-point connector J4. The design includes selectable jumpers for RS485 bus termination
resistors selection (JP10, JP11, JP12).
Figure 4-7.
RS485
4.3.8
Display Interface
The SAM3S-EK carries a TFT Transmissive LCD module with touch panel, FTM280C34D. Its integrated
driver IC is ILI9325. The LCD display area is 2.8 inches diagonally measured, with a native resolution of
240 x 320 dots.
4.3.8.1
LCD Module
The LCD module gets reset from the NRST signal. As explained, this NRST is shared with the JTAG port
and the push-button BP1. The LCD chip select signal is connected to NCS1; the jumper JP13 can dis-
connect it so that this PIO line is available for other custom usage.
The SAM3S communicates with the LCD through PIOC where an 8-bit parallel “8080-like” protocol data
bus has to be implemented by software.
PA25
PA24
PA21
PA22
PA2
3
FGND
DGND
+
3
V
3
DGND
+
3
V
3
+
3
V
3
DGND
R
3
6
0R
R
3
6
0R
C
3
4
100nF
C
3
4
100nF
C
3
5
100nF
C
3
5
100nF
C
3
6
100nF
C
3
6
100nF
R
3
2
47K
R
3
2
47K
MN5
ADM
33
12EARU
MN5
ADM
33
12EARU
C1+
6
C1-
20
C2+
2
C2-
4
C
3
+
24
C
3
-
22
VCC
3
V+
1
V-
21
GND
2
3
S
D
19
EN
5
T1IN
7
T1OUT
1
8
R1IN
15
R1OUT
10
T2IN
8
T2OUT
17
R2IN
14
R2OUT
11
T
3
IN
9
T
3
OUT
16
R
3
IN
1
3
R
3
OUT
12
R
38
0R
R
38
0R
C
3
1
4.7
u
F
C
3
1
4.7
u
F
C
3
2
100nF
C
3
2
100nF
R
3
5
0R
R
3
5
0R
C
3
7
100nF
C
3
7
100nF
C
33
100nF
C
33
100nF
J5
J5
5
4
3
2
1
9
8
7
6
10
11
R
3
4
0R
R
3
4
0R
R
33
0R
R
33
0R
R
3
1
0R
R
3
1
0R
R
3
7
47K
R
3
7
47K
PA22
PA24
PA25
PA21
PA2
3
DGND
+
3
V
3
+
3
V
3
+
3
V
3
DGND
FGND
MN4
ADM
3
4
8
5ARZ
MN4
ADM
3
4
8
5ARZ
RO
1
RE
2
DE
3
DI
4
VCC
8
GND
5
A
6
B
7
R2
8
0R
R2
8
0R
R
3
0
DNP
R
3
0
DNP
J4
J4
1
2
3
R29
120R
R29
120R
C
3
0
100nF
C
3
0
100nF
R26
0R
R26
0R
JP11
JP11
JP12
JP12
JP10
JP10
R27
0R
R27
0R
R2
3
DNP
R2
3
DNP
R25
DNP
R25
DNP
R24
DNP
R24
DNP
