10
9120A–AUTO–01/08
ATA6831/ATA6832 Driver ICs
6.
Applications
6.1
Demonstration Application
A typical demonstration application consists of a dual full bridge arrangement with microcontrol-
ler and watchdog to control two DC motors. Such dual H-bridge arrangement with common
mid-rail allows independent control of the motors for both rotation directions. Enter the appropri-
ate dataword according to
to set the required function. Instead of HSx and
LSx, the corresponding bits PHx and PLx can be used to control the motor speed by an external
PWM signal.
When operating in a safety-critical environment, the use of a separate watchdog IC is recom-
mended (for example U5021M).
If OLD is activated, the open-load detection is active for all outputs stages that are currently
switched off. A pull-up current for each high-side switch and a pull-down current for each
low-side switch is turned on (open-load detection current IHS1-3, ILS1-3). If VVS-VHS1-3 or
VLS1-3 is lower than the open load detection threshold, an open-load is detected: in the output
register the corresponding bit of the appropriate output is set to high.
If no outputs were activated, all low-side drivers of half bridges are detected as open loads. This
behavior is caused by the low-side open-load-detection current being larger than its high-side
counterpart. This configuration ensures that with half-bridge or H-bridge applications the
open-load detection also works in a well-defined way. If, for example, an open load at motor M1
should be detected, HS1 or HS2 has to be switched “on”, while the diametrical low-side output
register LS2 and LS1 respectively has to be evaluated.
If INH is activated by software inhibit bit SI, all activated loads are switched off, but the input and
output registers remain set.
Short-circuit detection can easily be demonstrated by intentional false activation of the
half-bridge components, for example, HS1 and LS1. This causes the OVL bit in the output regis-
ter to be set. Depending on the OCS bit, the affected outputs are switched off either by reaching
overtemperature or by reaching overcurrent. The corresponding status bits in the output register
are set to low. The OVL bit can be reset, and the disabled outputs can be re-enabled by activat-
ing the SRR bit. Please note that such activation of SRR only initiates a reset pulse, not a
permanent reset state.
The overtemperature prewarning is visible at the TP bit. When the CS pin is set to low, the pre-
warning information is visible in real time at the DO pin because TP is the first bit of output
register. Consequently, the TP bit is not buffered.
In case of overtemperature shutdown only overheated output switches off. The other outputs are
not touched. The dedicated output cannot be switched on again until activating the SRR bit.
As all high-side drivers are internally connected to their low-side counterparts in order to form a
half-bridge, switching from HS active to LS active or vice versa with a single programming
sequence could potentially imply some shoot-through current peak across both drivers during
the switching operation. The intelligent internal timing of ATA6831 guarantees that such cross-
over currents are avoided.
