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8068C–AVR–06/08
XMEGA A3
24. ADC - 12-bit Analog to Digital Converter
24.1
Features
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Two ADCs with 12-bit resolution
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2 Msps sample rate for each ADC
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Signed and Unsigned conversions
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4 result registers with individual input channel control for each ADC
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8 single ended inputs for each ADC
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8x4 differential inputs for each ADC
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Software selectable gain of 2, 4, 8, 16, 32 or 64
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Software selectable resolution of 8- or 12-bit.
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Internal or External Reference selection
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Event triggered conversion for accurate timing
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DMA transfer of conversion results
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Interrupt/Event on compare result
24.2
Overview
XMEGA A3 devices have two Analog to Digital Converters (ADC), see
The two ADC modules can be operated simultaneously, individually or synchronized.
The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capa-
ble of converting up to 2 million samples per second. The input selection is flexible, and both
single-ended and differential measurements can be performed. The ADC can provide both
signed and unsigned results, and an optional gain stage is available to increase the dynamic
range of the ADC.
It is a Successive Approximation Result (SAR) ADC. A SAR ADC measures one bit of the con-
version result at a time. The ADC has a pipeline architecture. This means that a new analog
voltage can be sampled and a new ADC measurement started on each ADC clock cycle. Each
sample will be converted in the pipeline, where the total sample and conversion time is seven
ADC clock cycles for 12-bit result and 5 ADC clock cycles for 8-bit result.
ADC measurements can be started by application software or an incoming event from another
peripheral in the device. Four different result registers with individual channel selection (MUX
registers) are provided to make it easier for the application to keep track of the data. It is also
possible to use DMA to move ADC results directly to memory or peripherals.
Both internal and external analog reference voltages can be used. An accurate internal 1.0V
reference is available.
