cleared or locked for user convenience. A set of Interrupt Flag and Status registers informs the user on
the status of the violation in the peripherals. In addition, slaves bus errors can be also reported in the
cases where reserved area is accessed by the application.
12.5.2. Basic Operation
12.5.2.1. Initialization
After reset, the PAC is enabled.
12.5.2.2. Enabling and Resetting
The PAC is always enabled after reset.
Only a hardware reset will reset the PAC module.
12.5.2.3. Operations
The PAC module allows the user to set, clear or lock the write protection status of all peripherals on all
Peripheral Bridges.
If a peripheral register violation occurs, the Peripheral Interrupt Flag n registers (INTFLAGn) are updated
to inform the user on the status of the violation in the peripherals connected to the Peripheral Bridge n (n
= A,B,C ...). The corresponding Peripheral Write Control Status n register (STATUSn) gives the state of
the write protection for all peripherals connected to the corresponding Peripheral Bridge n. Refer to the
for details.
The PAC module reports also the errors occurring at slave bus level when an access to reserved area is
detected. AHB Slave Bus Interrupt Flag register (INTFLAGAHB) informs the user on the status of the
violation in the corresponding slave. Refer to the
for details.
12.5.2.4. Peripheral Access Errors
The following events will generate a Peripheral Access Error:
•
Protected write: To avoid unexpected writes to a peripheral's registers, each peripheral can be write
protected. Only the registers denoted as “PAC Write-Protection” in the module’s datasheet can be
protected. If a peripheral is not write protected, write data accesses are performed normally. If a
peripheral is write protected and if a write access is attempted, data will not be written and
peripheral returns an access error. The corresponding interrupt flag bit in the INTFLAGn register will
be set.
•
Illegal access: Access to an unimplemented register within the module.
•
Synchronized write error: For write-synchronized registers an error will be reported if the register is
written while a synchronization is ongoing.
When any of the INTFLAGn registers bit are set, an interrupt will be requested if the PAC interrupt enable
bit is set.
Related Links
on page 116
12.5.2.5. Write Access Protection Management
Peripheral access control can be enabled or disabled by writing to the WRCTRL register.
The data written to the WRCTRL register is composed of two fields; WRCTRL.PERID and WRCTRL.KEY.
The WRCTRL.PERID is an unique identifier corresponding to a peripheral. The WRCTRL.KEY is a key
value that defines the operation to be done on the control access bit. These operations can be “clear
protection”, “set protection” and “set and lock protection bit”.
The “clear protection” operation will remove the write access protection for the peripheral selected by
WRCTRL.PERID. Write accesses are allowed for the registers in this peripheral.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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