Atmel ATmega128RFR2 Скачать руководство пользователя страница 7

    

    

    

    

    

    

    

 

   

 

 

 

 

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8393CS-MCU Wireless-09/14 

ATmega256/128/64RFR2 

 

3.2.22 CLKI 

Input  to  the  clock  system.  If  selected,  it  provides  the  operating  clock  of  the 
microcontroller. 

3.3 Unused Pins 

Floating  pins  can  cause  power  dissipation  in  the  digital  input  stage.  They  should  be 
connected  to  an  appropriate  source.  In  normal  operation  modes  the  internal  pull-up 
resistors  can  be  enabled  (in  Reset  all  GPIO  are  configured  as  input  and  the  pull-up 
resistors are still not enabled). 

Bi-directional I/O pins shall not be connected to ground or power supply directly. 

The  digital  input  pins  TST  and  CLKI  must  be  connected.  If  unused  pin  TST  can  be 
connected to AVSS while CLKI should be connected to DVSS. 

Output  pins  are  driven  by  the  device  and  do  not  float.  Power  supply  pins  respective 
ground supply pins are connected together internally. 

XTAL1 and XTAL2 shall never be forced to supply voltage at the same time. 

3.4 Configuration summary 

According  to  the  application  requirements  a  variable  memory  size  allows  to  optimize 
current consumption and leakage current. 

Table 3-1 

Memory Configuration 

Device 

Flash 

EEPROM 

SRAM 

ATmega256RFR2 

256KB 

8KB 

32KB 

ATmega128RFR2 

128KB 

4KB 

16KB 

ATmega64RFR2 

64KB 

2KB 

8KB 

 

Package  and  associated  pin  configuration  are  the  same  for  all  devices  providing  full 
functionality to the application. 

Table 3-2 

System Configuration 

Device 

Package 

GPIO 

Serial IF 

ADC channel 

ATmega256RFR2 

QFN 

38 

2 USART, SPI, TWI 

ATmega128RFR2 

QFN 

38 

2 USART, SPI, TWI 

ATmega64RFR2 

QFN 

38 

2 USART, SPI, TWI 

 

The devices are optimized for applications based on the ZigBee and the IEEE 802.15.4 
specification. Having application stack, network layer, sensor interface and an excellent 
power control combined in a single chip many years of operation should be possible. 

Table 3-3 

Application Profile 

Device 

Application 

ATmega256RFR2 

Large Network Coordinator / Router for IEEE 802.15.4 / ZigBee Pro  

ATmega128RFR2 

Network Coordinator / Router for IEEE 802.15.4 

ATmega64RFR2 

End node device / network processor 

 

Содержание ATmega128RFR2

Страница 1: ...al Interface Two Programmable Serial USART Byte Oriented 2 wire Serial Interface Advanced Interrupt Handler and Power Save Modes Watchdog Timer with Separate On Chip Oscillator Power on Reset and Low...

Страница 2: ...fter the device is characterized 1 PF3 ADC3 DIG4 PF2 ADC2 DIG2 2 3 PF5 ADC5 TMS PF4 ADC4 TCK 4 5 PF7 ADC7 TDI PF6 ADC6 TDO 6 7 RFP AVSS_RFP 8 9 AVSS_RFN RFN 10 11 RSTN TST 12 13 14 RSTON PG0 DIG3 56 5...

Страница 3: ...re combines a rich instruction set with 32 general purpose working registers All 32 registers are directly connected to the Arithmetic Logic Unit ALU Two independent registers can be accessed with one...

Страница 4: ...rupt or hardware reset In Power save mode the asynchronous timer continues to run allowing the user to maintain a timer base while the rest of the device is sleeping The ADC Noise Reduction mode stops...

Страница 5: ...ted digital supply voltage internally generated 3 2 5 DVSS Digital ground 3 2 6 AVSS Analog ground 3 2 7 Port B PB7 PB0 Port B is an 8 bit bi directional I O port with internal pull up resistors selec...

Страница 6: ...Port G pins that are externally pulled low will source current if the pull up resistors are activated The Port G pins are tri stated when a reset condition becomes active even if the clock is not runn...

Страница 7: ...4 Configuration summary According to the application requirements a variable memory size allows to optimize current consumption and leakage current Table 3 1 Memory Configuration Device Flash EEPROM S...

Страница 8: ...nterface The alternate pin function External Memory interface using Port A and Port C is not implemented due to the missing ports The large internal data memory SRAM does not require an external memor...

Страница 9: ...DD CB2 C1 C2 B1 RF C4 25 26 27 28 29 30 31 32 16 14 13 12 11 10 9 15 64 54 55 49 50 51 52 53 33 34 35 36 37 38 39 40 RSTON XTAL 32kHz CX3 CX4 CLKI DEVDD DVSS DEVDD PE7 DVSS DEVDD PF0 PF7 PG0 PG5 PD0 P...

Страница 10: ...layout of the PCB and any leakage path must be avoided Crosstalk and radiation from switching digital signals to the crystal pins or the RF pins can degrade the system performance The programming of...

Страница 11: ...F AVSS AVSS RFP RFN AVSS TST DVSS DVDD DVDD XTAL2 DEVDD DVSS AVDD EVDD AVSS XTAL1 41 42 43 44 45 46 47 48 PB0 DVSS PE0 PB7 CB3 CB4 RSTN VDD XTAL CX1 CX2 CB1 VDD CB2 25 26 27 28 29 30 31 32 16 14 13 12...

Страница 12: ...re referring to this document The referring revision in this section are referring to the document revision Rev 8393CS MCU Wireless 09 14 1 Content unchanged recreated for combined release with the da...

Страница 13: ...ns 2 2 Disclaimer 2 3 Overview 3 3 1 Block Diagram 3 3 2 Pin Descriptions 5 3 3 Unused Pins 7 3 4 Configuration summary 7 3 5 Compatibility to ATmega1281 2561 8 4 Application Circuits 9 4 1 Basic Appl...

Страница 14: ...tion with the sale of Atmel products EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED...

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