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4929B–AUTO–01/07

ATA6264 [Preliminary]

28. Table of Contents

Features ..................................................................................................... 1

Description ............................................................................................... 1

1.1

Block Description .................................................................................................3

1.1.1

Integrated Boost Converter EVZ .....................................................................3

1.1.2

Integrated Buck Converter VSAT ....................................................................3

1.1.3

Integrated Buck Converter VCORE ................................................................3

1.1.4

Linear Regulator VPERI ..................................................................................3

1.1.5

Blocks Included ...............................................................................................3

Pin Configuration ..................................................................................... 4

Absolute Maximum Ratings .................................................................... 6

Functional Range ..................................................................................... 8

4.1

Protection Against Substrate Currents .................................................................9

Supply Currents ..................................................................................... 10

5.1

Discharger Circuit ...............................................................................................11

5.2

Initial Programming of the ATA6264 ..................................................................11

5.3

Start-up and Power-down Procedure .................................................................14

5.3.1

Start-up Procedure if VVCORE is Programmed to Be 5V or 2.5V ................ 15

5.3.2

The Power-down Procedure Takes Place in Different Phases .....................15

5.3.3

Start-up Procedure if VVCORE Programmed to Be 1.88V ...........................16

5.3.4

The Power-down Procedure for VVCORE is Programmed to be 1.88V .......17

Power Supply Sequencing .................................................................... 18

Charge Pump .......................................................................................... 20

GKEY Function ....................................................................................... 22

EVZ Step-up Regulator .......................................................................... 24

VSAT Power Supply ............................................................................... 30

VPERI Power Supply ............................................................................. 33

VCORE Power Supply ........................................................................... 35

USP Comparator for General Purpose ................................................. 39

Reference Voltage and Reference Current Generation ...................... 40

Reset Function (Pin RESQ and Pin RESQ2) ........................................ 41

Watchdog Function ............................................................................... 47

Содержание ATA6264

Страница 1: ...on of airbag power supplies for future airbag systems tailored to the needs of the automotive industry It is designed in Atmel s 0 8 micron BCDMOS technology ATA6264 contains all the necessary blocks to supply the microcontroller the firing capacitors and peripheral components of the airbag system The power supply specifically fulfills the power requirements of dual voltage microcontrollers used i...

Страница 2: ...VZ Regulator VSAT Regulator K30 GEVZ SVSAT VSAT COMCOI COMCOO VCORE SVCORE VPERI SVPERI COMSATI COMSATO COMEVZO FBEVZ EVZ GNDB OCEVZ GKEY Logic UZP USP AMUX ISO9141 IASG Serial Interface Watchdog Reset RESQ2 IASG1 IASG2 IASG4 ISENS GNDA UZP IASG5 IASG3 K2 K1 GNDD RESQ MOSI VSAT SVSAT VBATT VBATT CP_OUT IREF VINT USP SCLK SSQ CP K15 MISO RxD2 TxD1 RxD1 TxD2 ...

Страница 3: ...ser can program the voltage via an OTP system With a sophisticated power sequencing concept of VCORE and VPERI ATA6264 sup ports dual voltage supply microcontrollers so that under all conditions the voltage difference between the two linear regulator voltages never drops below a defined value This measure guarantees the safe operation of the system 1 1 5 Blocks Included A general purpose comparato...

Страница 4: ...nterface 4 K2 Bus line of 2nd ISO9141 interface 5 IASG1 Output of voltage source 1 6 IASG2 Output of voltage source 2 7 IASG3 Output of voltage source 3 8 IASG4 Output of voltage source 4 9 IASG5 Output of voltage source 5 10 ISENS Output of the current mirror from the IASGx interface 11 TXD1 Data input of the 1st ISO9141 interface 12 RESQ Reset output 13 RXD2 Data output of the 2nd ISO9141 interf...

Страница 5: ...on to car battery via the ignition key 34 COMSATO Output of the VSAT externally compensated error amplifier 35 COMCOI Input of the VCORE externally compensated error amplifier 36 COMCOO Output of the VCORE externally compensated error amplifier 37 CP OUT Switchable output of charge pump voltage 38 SVCORE Output of VCORE regulator power transistor 39 CP Charge pump output 40 FBEVZ Input for externa...

Страница 6: ...t pins connected directly or indirectly to the car battery IASG1 IASG2 IASG3 IASG4 IASG5 Any combination of one or more pins applied with any voltage between the limits Voltage necessary to drive 40 mA stored in 20 µH 45 V Voltage at ECU internal pins FBEVZ EVZ VSAT Any combination of one or more pins applied with any voltage between the limits 0 3 45 V Maximum rate of change at pin VSAT 1 V µs Vo...

Страница 7: ... HBM AEC Q100 002 CDM ESD STM5 3 1 1999 1500 500 750 V V V 3 Absolute Maximum Ratings Continued Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to ab...

Страница 8: ...0 3 5 5 V 1 6 Supply voltage CP CP OUT 0 3 50 V 1 7 Voltage on digital I O pins 0 3 5 5 V 1 8 Voltage on pins SVSAT SVCORE 1 0 40 V 1 9 Voltage on pins UZP ISENS COMCOI COMCOO COMSATO COMSATI COMEVZO FBEVZ IREF VINT 0 3 5 5 V 1 10 Voltage on pins GEVZ OCEVZ 0 3 10 V 1 11 Voltage on pin SVPERI 0 3 6 V 1 12 Voltage on pins IASGx x 1 to 5 Voltage necessary to drive 40 mA stored in 20 µH 40 V 1 14 Tem...

Страница 9: ...ns might occur IASG interface IASG1 IASG2 IASG3 IASG4 IASG5 USP comparator USP If substrate currents occur it is guaranteed by design that no disturbance and malfunction of the following blocks and functions will happen No disturbance of RESET block No voltage changes of any regulators outside of their tolerances No impact on digital circuitry for example changes of latches status register etc No ...

Страница 10: ...nt at K30 Normal mode 18V VK30 40V VEVZ VK30 VK15 4 15V or KEYLATCH ON SVCORE open AMUX Measurement K30 active K30 IK30 0 10 mA A 2 2 Supply current at EVZ Startup mode 0V VEVZ 40V VSAT VPERI VCORE 0V VK30 5V VK15 4 15V SVCORE and SVSAT open EVZ IEVZ 0 5 mA A 2 2a Supply current at EVZ Normal mode 0V VEVZ 40V VPERI and VCORE Reset Threshold VEVZ VK30 VSAT 10V VK30 5V VK15 4 15V SVCORE and SVSAT op...

Страница 11: ... a discharger circuit which avoids such unwanted effects If VK30 exceeds a threshold value of approximately 26 8V the blocking capacitor is discharged via an integrated resistor until VK30 again falls below the threshold Figure 5 1 Discharger Circuit 5 2 Initial Programming of the ATA6264 The ATA6264 supports different output voltages at the VSAT VPERI and the VCORE regula tors In addition differe...

Страница 12: ... 0 1 0 1 88V 3 3V 9 1V 0 0 1 1 1 88V 3 3V 10 4V 0 1 0 0 2 5V 3 3V 7 8V 0 1 0 1 2 5V 3 3V 9 1V 0 1 1 0 2 5V 3 3V 10 4V 0 1 1 1 1 88V 5V 7 8V 1 0 0 0 1 88V 5V 9 1V 1 0 0 1 1 88V 5V 10 4V 1 0 1 0 2 5V 5V 7 8V 1 0 1 1 2 5V 5V 9 1V 1 1 0 0 2 5V 5V 10 4V 1 1 0 1 5V 5V 7 8V 1 1 1 0 5V 5V 9 1V 1 1 1 1 5V 5V 10 4V Set to 0 Set to 1 EXT No external transistor at VPERI default External transistor at VPERI ap...

Страница 13: ...xecuted Figure 5 2 Programming Sequence Remove all voltages and pinloads to get out of Test mode Transmit IP command A9xx h via SPI to configure ATA6264 Wait 1 ms Wait until VSAT 11 7V Transmit 5A5A h via SPI to Enable Testmode Set RESQ and TxD1 to GND and RESQ2 and TxD2 to 5V Apply 12V at K15 K30 and5V at VPERI Contact pins RESQ RESQ2 TxD1 TxD2 SSQ MOSI SCLK VPERI K15 K30 ...

Страница 14: ...or hooked up to pin EVZ Figure 5 3 Block Diagram Start up and Power down Procedure VCP VCP K30 EVZ VEVZ VVSAT VVPERI Comp VEVZ K15GOOD VK15 3V to 4 15V 40 mV to 175mV Hysteresis Serial interface KEY LATCH VSAT VCP Comp CORE_EN VPERI 1 25V to 1 7V 50 mV to 150 mV Hysteresis Comp VSATGOOD VSAT 6 77V to 7 2V 200 mV to 500 mV Hysteresis Comp VEVZ VCP K15 K30 CP GEVZ EVZEN CORESWAP 5V IREF lost signal ...

Страница 15: ...ocedure Takes Place in Different Phases Phase1 If the ignition key is switched off K15 voltage will vanish at pin K15 If the serial inter face command KEYLATCH is not set the EVZ regulator stops working The external charge pump is still working because EVZ is above VSAT and the VSAT regulator is not in Perma nent on mode The charge pump voltage still supplies the VSAT regulator and the VCORE regul...

Страница 16: ...laced by the serial interface command KEYLATCH which can be set by the serial interface Phase2 If VEVZ is larger than 7 5V to 9V the VSAT regulator starts operating Phase3 After VVSAT has reached 6 77V to 7 2V the VPERI regulator starts working Phase4 If VVPERI is higher than 1 25V to 1 7V the VCORE regulator will be enabled t VK30 3V to 4 15V 3V to 4 15V 5 5V to 6 2V too low EVZ voltage VSAT goes...

Страница 17: ...reaches Permanent on mode the external charge pump stops working and the VSAT voltage falls analog to the EVZ voltage If the voltage at VSAT is below 6 27V to 7V the VPERI regulator will be switched off Depending on the charge pump voltage the VCORE regulator stops working The power sequencing function for the VPERI regulator is still active and guarantees a maximum voltage difference between VPER...

Страница 18: ...s below a hysteresis value Figure 6 1 Example for Incorrect Ramp Up Necessary for operation VEVZ 0V to 40V VINT 3 7V to 5 47V Operating conditions of all other supply pins VK30 VVSAT VVPERI and VVCORE are within functional range limits Tj 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 1 88V Not allowed area VVPERI VVCORE 2 8V 3 3V VVPERI VVCORE t t Table 6 1 Electrical...

Страница 19: ... VCP Comp VSATGOOD VSAT 6 77V to 7 2V VCORE Regulator 200 mV to 500 mV Hysteresis Comp VEVZ VCP K15 K30 CP GEVZ EVZEN CORESWAP 5V IREF lost signal VK30 3 85V to 5V 50 mV to 150 mV Hysteresis VSAT driver SVSAT EVZ VVCORE VCORE SVCORE VK30 IP VEVZ driver Comp K30GOOD VPERI driver Delta 2 8V VPERI SVPER IP VK30 6 1V to 8 1V ON 0 5V to 1V Hysteresis Comp EVZGOOD VEVZ 7 5V to 9V ON VEVZ 5 5V to 6 2V OF...

Страница 20: ...l series resistor is recom mended to suppress spikes during switching of the SVSAT The CP block is supplied by EVZ and VSAT voltage and starts to operate as soon as the thresholds for VK15 K30 and EVZ are achieved An additional start up circuitry is implemented to support the VSAT driver during the start up phase thus enabling a reliable system startup The charge pump has an output CP OUT to suppl...

Страница 21: ... 50 µs A 6 13 Current limitation at pin CP OUT CP OUT ICP OUT 0 8 4 2 mA A 6 14 Voltage difference VCP VEVZ for detecting wrong CP Note Threshold is in the range of 5V to 7V CP VDiff 5 V A 6 15 Time between wrong CP voltage and valid data in status register CP td 0 50 µs A 6 16 Voltage difference VCP OUT VEVZ for detecting wrong CP OUT Note Threshold is in the range of 5V to 7V CP OUT VDiff 5 V A ...

Страница 22: ...erface driven latch command and the K30 voltage determines the EVZ Enable signal In order to achieve the Switch Function of the GKEY function a transformer has to be used Note 1 Less than the value shown in number 7 3 of Table 8 2 on page 23 2 Greater than the value shown in number 7 3 of Table 8 2 on page 23 3 Greater than the value shown in number 7 1 of Table 8 2 on page 23 Figure 8 1 Applicati...

Страница 23: ...Parameters Test Conditions Pin Symbol Min Typ Max Unit Type 7 1 Voltage level at K15 to enable the EVZ regulator VK15 increasing VK30 5V K15 VK15 3 4 15 V A 7 2 Hysteresis at K15 to disable the EVZ regulator K15 VK15 40 175 mV A 7 3 Voltage level at K30 to enable the EVZ regulator VK30 increasing VK15 4 15V K30 VK30 3 85 5 V A 7 4 Hysteresis at K30 to disable the EVZ regulator K30 VK30 50 150 mV A...

Страница 24: ...nnel power FET with a fixed frequency of 100 kHz A driver stage for the external FET is integrated into the ATA6264 The current limita tion of the external FET is implemented by using an external resistor in series between the source connection of the external FET and GND sensing the voltage drop at this resistor via the pins OCEVZ and GNDA The reference section provides a reference voltage of 1 2...

Страница 25: ...ically to pin FBEVZ The remaining voltage at FBEVZ causes the regulator to switch off The output of the error amplifier is compared with a periodic linear ramp of a saw tooth genera tor by the PWM comparator A logic signal with variable pulse width is generated which controls the PWM frequency of the external FET A maximum duty cycle is determined by the duration of the falling ramp of the saw too...

Страница 26: ...al transistor is switched off During startup the voltage on pin EVZ is too low and the PWM comparator requires a duty cycle of more than 90 Due to an increasing inductance current after several periods the overcur rent sensor becomes active and reduces the maximum duty cycle to improve magnetic energy transfer Figure 9 4 Output Current During Start up A capacitance of 10 mF or more may be applied ...

Страница 27: ...ble 8 2 on page 23 A 8 7 Voltage at pin GEVZ to switch through the external driver VK30 3 85V to 5V ON threshold GEVZ VGEVZ VK30 0 5V VK30 V A 8 8 Voltage at pin GEVZ to switch through the external driver VK30 7V GEVZ VGEVZ 6 10 V A 8 9 Driving current at pin GEVZ to switch through the external driver VGEVZ 5V GEVZ IGEVZ 600 80 mA A 8 10 Gate charge delivered to the external FET VGEVZ 5V GEVZ QGEV...

Страница 28: ...boost converter output stage GEVZ tdoff 50 150 ns A 8 25 Switch off fall time for the boost converter output stage Time between 4 5V and 0 5V at GEVZ CGEVZ 2 nF GEVZ tfoff 10 100 ns A 8 26 Leakage current at pin OCEVZ OCEVZ IOCEVZ 10 10 µA A 8 27 Leakage current at pin FBEVZ FBEVZ IOCEVZ 10 10 µA A 8 28 Switch on threshold via FBEVZ Band gap tolerance included FBEVZ VFBEVZ 1 20 1 24 V A 8 29 Switc...

Страница 29: ... ICOMEVZO 100 µA COMEVZO VCOMEVZO 0 0 2 V A 8 38 Output voltage high on pin COMEVZO ICOMEVZO 100 µA COMEVZO VCOMEVZO VINT 0 3V VINT V A GNDA GNDB Disconnect 8 40 GNDA lost detection VGNDA VGNDD GNDA VGNDA 0 2 0 4 V A 8 41 Delay for GNDA lost detection GNDA td 10 50 µs A 8 42 GNDB lost detection VGNDB VGNDD GNDB VGNDB 0 2 0 4 V A Table 9 1 Electrical Characteristics Continued EVZ Step up Regulator ...

Страница 30: ... that current mode controlled converters exhibit sub harmonic oscillations when operating at duty cycles higher than 50 a slope compensation which adds an artificial ramp to the comparator is implemented If the regulator input voltage at pin EVZ is too low the regulator switches to a duty cycle of 100 Permanent on mode The VSAT voltage can be programmed via the serial interface to one of three dif...

Страница 31: ... output transistor SVSAT RSVSAT 1 Ω A 9 8 Output voltage 1 only at VPERI 3 3V Band gap tolerance included VSAT VVSAT1 4 7 8 4 V A 9 9 Output voltage 2 VVSAT2 programmed Band gap tolerance included VSAT VVSAT2 4 9 1 4 V A 9 10 Output voltage 3 VVSAT3 programmed Band gap tolerance included VSAT VVSAT3 4 10 4 4 V A 9 11 Output transistor switch on time Time between reaching 0 1 VEVZmax VSVSATmin and ...

Страница 32: ... bandwidth 2 MHz D 9 23 Output voltage low ICOMSATO 165 µA COMSATO VCOMSATO 0 0 3 V A 9 24 Output voltage high ICOMSATO 85 µA COMSATO VCOMSATO VVINT 0 6V VVINT V A 9 25 Leading edge blanking time tblank 150 200 ns D 9 26 Slope of artificial ramp for slope compensation dV dt 150 1 240 1 mV µs D 9 27 VSAT loss detection threshold 2 ILoad 0 1 5 mA D Table 10 1 Electrical Characteristics Continued VSA...

Страница 33: ...ent protection If pin VPERI is disconnected the regulator is switched off and RESQ RESQ2 are set to low Figure 11 1 Functional Principle of the VPeripheral Regulator If a higher current capability of the regulator is requested or if the power dissipation of the linear regulator is too high an external transistor can boost the regulator Figure 11 2 Functional Principle of the VPERI Regulator With E...

Страница 34: ...T 0 2 0 5 V A 10 3 Output voltage 1 VVPERI1 programmed band gap tolerance included VPERI VVPERI 3 6 5 4 V A 10 4 Output voltage 2 VVPERI2 programmed band gap tolerance included VPERI VVPERI 4 3 3 3 V A 10 5 Output current VVSAT 7 5V to 12 5V VPERI IVPERI 100 mA A 10 6 Short circuit current VPERI IVPERI 200 110 mA A 10 7 Line regulation VVSAT 8V to 12 5V IPERI 1 mA to 100 mA IPERI is constant durin...

Страница 35: ... is detected at the pin VCORE the transistor is switched off immediately 3 If the feedback voltage at the pin VCORE is missing disconnected pin the regulator is switched off Figure 12 1 Functional Principle of the VCORE Regulator In order to trim the compensation of the regulation loop and to improve the behavior at load changes pin COMCOO has to be connected to COMCOI via a compensation network B...

Страница 36: ...1 3 Switch on time via pin EVZ SVCORE tSVCORE 0 20 µs A 11 4 Switch off time via pin EVZ SVCORE tSVCORE 0 10 µs A 11 5 Regulator switching frequency See numbers 8 1 and 8 2 of Table 9 1 on page 27 SVCORE fSVCORE A 11 6 Output current limit SVCORE ISVCORE 0 7 0 9 A A 11 7 RDson of output transistor SVCORE RSVCORE 1 2 Ω A 11 8 Output voltage 1 VVCORE1 programmed band gap tolerance included VCORE VVC...

Страница 37: ...maximum under on condition SVCORE tSVCOREoff 0 0 5 µs A 11 16 Leakage current at pin SVCORE Output transistor off SVCORE ISVCORE 10 10 µA A Error Amplifier 11 17 Maximum output current at pin COMCOO sinking to low COMCOO ICOMCOO 200 3000 µA A 11 18 Maximum output current at pin COMCOO sourcing to high COMCOO ICOMCOO 165 85 µA A 11 19 Input impedance at pin COMCOI VCORE 1 88V VCORE 2 5V 5V COMCOI R...

Страница 38: ...K30 increasing K30 VK30 6 1 8 1 V A 11 30 Hysteresis at K30 to switch VCORE supply from K30 to EVZ VVCORE 5V programmed VK30 decreasing K30 VK30 0 5 1 V A 11 31 Time to switch VCORE supply from EVZ to K30 or K30 to EVZ SVCORE tswitch 0 7 6 µs D 11 32 VCORE loss detection threshold 2 VCORE ILoad 0 1 mA D Table 12 1 Electrical Characteristics Continued VCORE Power Supply No Parameters Test Condition...

Страница 39: ... 47V Operating conditions of all other supply pins VSAT and VK30 are within functional range limits Tj 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Status register USP GNDA to AMUX 2 44V Table 13 1 Electrical Characteristics USP Comparator for General Purpose No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type 12 1 Input current at pin USP VUSP 2 44V USP I...

Страница 40: ...ther pins As defined in Section 4 Functional Range on page 8 Table 14 1 Truth Table for VINT State K30GOOD VK30 4 2V to 5V K15GOOD VK15 3V to 4V VEVZ VVINT 1 Low Low 0 OFF 2 High Low 0 OFF 3 Low High 0 OFF 4 High High VEVZ VK30 ON Supply K30 5 Low Low VEVZ 5 5V ON Supply EVZ only valid if VINT was already enabled via state 4 6 High Low VEVZ 5 5V ON Supply EVZ only valid if VINT was already enabled...

Страница 41: ...reset threshold and the VPERI reset threshold and the EVZ reset threshold signal EVZGOOD high have been reached If the watchdog circuitry does not detect a valid watchdog trigger the RESQ signal is set to low again If the watchdog was triggered successfully RESQ stays high and RESQ2 is also set to high In the case that an overvoltage at VCORE or VPERI is detected the voltages at pins RESQ and RESQ...

Страница 42: ...ommunication Re configure prescaler while 1 st and 2nd trigger watchdog command chip internal trigger window RESQ2 RESQ 16 ms 16 ms WD cyc WD cyc t t t t VCORE OK VPERI OK t t t any different SPI CMD re configure prescaler Trg Wdg CMD Trg Wdg CMD Trg Wdg CMD 4 ms 4 ms Watchdog cycle see pages 48 and 49 ...

Страница 43: ...nformation about regulator problems and results in a low level signal for RESQ RESQ2 Figure 15 3 Functional Principle of the Supervisor Circuit for VCORE Monitoring Values are Valid for VVCORE 1 88V and VVPERI 3 3V If the watchdog is triggered incorrectly RESQ and RESQ2 are set to low as well Voltage spikes on EVZ smaller than or equal to 10 µs to 20 µs do not influence the RESQ or RESQ2 pins If t...

Страница 44: ...fined low via resistor 1V to VVPERI OK X X X Low Low VVPERI OK VVCORE Not OK X X Low Low VVCORE OK EVZGOOD high VEVZ OK After startup no trigger has occurred High Low Correctly triggered trigger occurred 1st time High Low high Correctly triggered High High Incorrectly triggered High low High low X EVZGOOD low VEVZ Not OK X Low Low VEVZ VCORE VPERI WD logic Watchdog is triggered Other peri 3 3V Saf...

Страница 45: ...w VVCORE is set to 5V VCORE VVCORE 4 97 5 5 V A 14 6a Voltage difference reset threshold at VCORE see number 14 6 VVCORE VVCORE is set to 5V VCORE dVVCORE 0 17 0 7 V A 14 7 Overvoltage at pin VCORE to switch off the regulator and set RESQ to low VVCORE is set to 2 5V VCORE VVCORE 2 5 2 8 V A 14 7a Voltage difference reset threshold at VCORE see number 14 7 VVCORE VVCORE is set to 2 5V VCORE dVVCOR...

Страница 46: ... Output current high side RESQ RESQ2 RESQ RESQ2 are switched to high VRESQ VRESQ2 0V RESQ RESQ2 IRESQ IRESQ2 550 250 µA A 14 20 Output current low side RESQ RESQ2 RESQ RESQ2 are switched to high VRESQ VRESQ2 VVPERI RESQ RESQ2 IRESQ IRESQ2 4 10 mA A 14 21 Rise time RESQ RESQ2 30 pF external capacitive load RESQ RESQ2 tRESQ tRESQ2 4 0 µs A 14 22 Fall time RESQ RESQ2 30 pF external capacitive load RE...

Страница 47: ... set into its default state latches MISO status etc and RESQ is set to low Watchdog has to be triggered cyclically prescaler for repetition time is set via serial interface command Default 16 ms repetition time Figure 16 1 Watchdog Trigger Functional Principle Re configure prescaler during 1 st and 2nd trigger watchdog command Serial interface communication chip internal trigger window VCORE 4 8V ...

Страница 48: ...w to high trig ger window 25 means 4 ms trigger window for first trigger watchdog command After the first watchdog trigger the prescaler can be reconfigured within a specified time window 1 ms Only one configuration command is allowed in this time window For watchdog trigger handling the Serial Interface Reconfigure command can be chosen as a different serial interface com mand Any further configu...

Страница 49: ... trigger commands a different SPI command must be seen by the SPI decoder Figure 16 3 Watchdog Trigger Functional Principle Successful Watchdog Trigger Serial interface communication chip internal trigger window t_retrigger t_retrigger t_retrigger RESQ t t t inactive Additional SPI CMD Trg Wdg CMD Trg Wdg CMD Additional SPI CMD Trg Wdg CMD Additional SPI CMD Trg Wdg CMD 4 4 4 4 ...

Страница 50: ...munication chip internal trigger window t_retrigger 4 4 t_retrigger RESQ RESQ t t t 4 4 inactive inactive active active t_retrigger 4 4 t_retrigger t t t 4 4 inactive inactive active active Trg Wdg CMD Trg Wdg CMD Trg Wdg CMD Trg Wdg CMD Missing command serial interface additional Trg Wdg CMD Trg Wdg CMD Trg Wdg CMD Trg Wdg CMD command serial interface additional command serial interface additiona...

Страница 51: ...efined in Table 16 1 The status of the watchdog prescaler is indicated in the status register Description MSByte LSByte Hex Code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Configure prescaler 0 1 1 0 0 0 0 0 1 1 1 1 0 a b c 60Fx Table 16 1 Watchdog Prescaler Command Selection Bits Retrigger Time ms a b c 0 0 0 Set to default 16 ms 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 Set to default 16 m...

Страница 52: ...n of RESQ signal RESQ tRESQ 16 16 A 15 3 Start of first watchdog trigger window after rising edge at RESQ t 12 12 A 15 4 Maximum width of first watchdog trigger window t 8 8 A 15 5 Maximum time for prescaler configuration after first watchdog trigger command t 1 1 A 15 6 Programmed watchdog cycle tWD as set by prescaler default 16 ms tWD tWD A 15 7 Start of programmed watchdog window 75 tWD 75 tWD...

Страница 53: ...during 1 st and 2nd trigger watchdog command VCC 15 2 ms 15 4 ms 15 7 ms 15 5 ms 15 3 ms 15 6 ms 15 8 ms 15 9 ms 4 75V 5 0V Serial interface communication chip internal trigger window RESQ t t t t re configure prescaler Trg Wdg CMD any different serial interface command Trg Wdg CMD Trg Wdg CMD ...

Страница 54: ...transistors switched on or off by the serial interface In this mode a diagnosis of the pins K1 and K2 via the analog multiplexer is possible The K1 and K2 outputs include an internal current limitation and overtemperature protection circuit Figure 17 1 Functional Principle of the LIN ISO 9141 Interfaces Necessary for operation VEVZ 9V to 40V VK30 5 5V to 40V VVPERI Reset threshold VVCORE Reset thr...

Страница 55: ...11 RxDx voltage drop high side x 1 2 with IRxDx 0 µA to 500 µA RxDx VRxDx VVPERI 0 8 VVPERI V A 16 12 RxDx voltage drop low side x 1 2 IRxDx 0 mA to 1mA RxDx VRxDx 0 0 4 V A 16 13 RxDx high side output current x 1 2 VRxDx 0V RxDx IRxDx 1 1 0 2 mA A 16 14 RxDx low side output current x 1 2 VRxDx VVPERI RxDx IRxDx 1 4 mA A 16 15 RxDx output rise time x 1 2 30 pF external load RxDx tRxDx 1 µs A 16 16...

Страница 56: ...f transmitter delay x 1 2 tSYM_Tx tPDtL tKfall tPDtH tKrise Kx tSYM_Tx 1 1 µs A 16 31 Symmetry of receiver propagation delay x 1 2 tSYM_Rx tPDkL tPDkH Kx tSYM_Rx 1 1 µs A LIN Bus Mode Necessary for Operation VK30 8V to 18V 16 32 Slew rate for rising and falling edge Measured between high level 0 8 VK30 and low level 0 2 VK30 RK1 1 kΩ to K30 CK1 3 3 nF to GNDB K1 dVK1 dt 1 3 V µs A 16 33 Maximum ba...

Страница 57: ...16 42 Kx switch off delay x 1 2 measured from rising edge of SSQ to VKx 0 9 VK30 RKx 250Ω to K30 CKx 3 3 nF to GNDB Kx tKx 10 µs A 16 43 Kx leakage current x 1 2 output driver deactivated AMUX measurement activated and deactivated K30 5 5V to 15V K30 15V to 25V K30 25V to 40V Kx IKx 10 10 10 100 160 260 µA µA µA A A A 16 44 Kx leakage current x 1 2 output driver deactivated AMUX measurement deacti...

Страница 58: ...sequently the current at pin IASGx is reduced until VISENS VVPERI This function can be used to reduce the current limitation of pin IASGx to values lower than the internal limit by choos ing an adequate external resistor at pin ISENS In this case the maximum current through pin IASGx can be calculated as or For high accuracy the IASGx current needs to be between 0 5 mA and 40 mA and the maxi mum I...

Страница 59: ...tched to 10V VINT 3 7V to 5 47V VCP VEVZ 7V Operating conditions of all other supply pins VK30 and VVSAT are within functional range limits Tj 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 CI A S G x 10 nF and 825Ω RISENS 5 kΩ Serial interface Serial interface UZP Current mirror Serial interface Analog multiplexer Short circuit protection 10 15 IASGx C 10 pF RIASGx I ...

Страница 60: ...A A 17 4 Maximum duration of voltage overshoot at IASGx x 1 to 5 with VIASGx 10V 0 5 mA RLOAD VIASGx 5V 40 mA IASGx tIASGx 30 µs A 17 5 Linear range for current mirror at IASGx x 1 to 5 0V VISENS 0 96 VPERI IASGx IIASGx 40 0 5 mA A 17 6 Internal current limitation at IASGx x 1 to 5 IASGx IIASGx 150 50 mA A 17 7 Current ratio 1 x 1 to 5 CR1x IIASGx IISENS 0V VISENS 0 96 VVPERI 40 mA IIASGx 0 5mA IA...

Страница 61: ...akage current VISENS 0V to 0 96 VVPERI ISENSE IISENSE 1 6 1 6 µA A 17 13 IASGx leakage current x 1 to 5 IASGx channel deactivated 0V VIASGx VEVZ IASGx IIASGx 1 6 1 6 µA A Table 18 1 Electrical Characteristics Continued Voltage Current Sources IASGx Sources No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Type means A 100 tested B 100 correlation tested C Characterized on samples D De...

Страница 62: ... of the measurement part inside the ATA6264 can be calculated using the following formula Figure 19 1 AMUX Tolerances In order to describe the behavior of the whole measurement properly the tolerance of the volt age divider ratio ratio tolerance and the offset tolerance of the UZP buffer VUZPoffset are defined in separate points The UZP buffer is defined in the following section Necessary for oper...

Страница 63: ... 7 Ratio VISENS VUZP VVPERI 0 2V VISENS 0 2V UZP Ratio 0 992 1 A 18 8 Ratio VK1 VUZP For VVPERI 5V 1 5V to 3V For VVPERI 5V 3V to 25V UZP Ratio 6 06 3 5 6 06 2 3 A A 18 8a Ratio VK1 VUZP For VVPERI 3 3V 1 5V to 3V For VVPERI 3 3V 3V to 25V UZP Ratio 9 16 3 5 9 16 2 3 A A 18 9 Ratio VK2 VUZP For VVPERI 5V 1 5V to 3V For VVPERI 5V 3V to 25V UZP Ratio 6 06 3 5 6 06 2 3 A A 18 9a Ratio VK2 VUZP For VV...

Страница 64: ...o VUZP UZP Ratio 0 1 VVPERI 2 A 18 19 Input voltage range for proper function of 10 or 14 6 divider VInput 6 40 V A 18 20 Input voltage range for proper function of 6 or 9 1 divider VInput 1 5 25 V A 18 21 Input voltage range for proper function of 4 and 2 divider VInput 4 6 V A 18 22 Input voltage range for proper function of 1 buffer VInput 0 2 VVPERI 0 2 V A 18 23 Ratio VREF VUZP 2 1 0 A Table ...

Страница 65: ...and has been sent Driver capability is typically 4 mA Figure 20 1 Functional Principle of the UZP Buffer Necessary for operation VPERI Reset threshold VCP 10V to 50V VVINT 3 7V to 5 47V Operating conditions of all other supply pins VK30 VEVZ VVSAT and VVCORE are within functional range limits TJ 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Driver circuitry Tristate n...

Страница 66: ...ing time Load 2 kΩ 22 nF low pass filter connected to pin UZP measured from rising edge of SSQ to 90 of VLow pass filter out UZP tUZP 250 µs A 19 5 Output resistance UZP RUZP 100 Ω A 19 6 Linear measurement range UZP VUZP 0 2 VVPERI 0 2 V A 19 7 Maximum output voltage VIASG5 switched via AMUX to UZP VIASG5 6V UZP VUZP VVPERI 50 mV VVPERI 50 mV V A 19 8 Output leakage current VUZP 0V to VVPERI UZP ...

Страница 67: ...supply pins VK30 VEVZ VVSAT VVPERI and VVCORE are within functional range limits Tj 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Table 21 1 Electrical Characteristics Chip Temperature Measurement No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type 20 1 Temperature coefficient of chip temperature sensor Chip temperature switched via AMUX to UZP UZP VUZP 4 3...

Страница 68: ... with SPI bus activities To ensure deactivation of the device in case of an open SSQ pin an internal current source is implemented to drive the SSQ pin to high level VPERI All commands independent of their function consist of 16 bits The serial interface includes a 16 bit input shift register 16 bit latches and a decoder logic block for the generation of the SPI command signals To suppress data tr...

Страница 69: ...ERI V A 21 19 Output voltage low level IMISO 0 mA to 1 mA MISO VL 0 0 4 V A 21 20 Output current high level driven to short circuit VVPERI 5V MISO IMISO 47 10 mA A 21 21 Output current low level sinking from VPERI level VVPERI 5V MISO IMISO 6 45 mA A 21 22 Input capacitance SSQ SCLK MOSI CIN 10 pF D 21 23 Output capacitance Switched off condition MISO CMISO 10 pF D 21 24 Leakage current Switched o...

Страница 70: ...t of Serial Interface Commands Command Latch Hex Description MSByte LSByte 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Command Option and Data NOP No 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Key latch Yes 3xxx See Table 22 3 on page 71 0 0 1 1 x x x x x x x x x x x x Watchdog No 6xxx See Table 22 4 on page 71 0 1 1 0 x x x x x x x x x x x x Switch commands Yes 9xxx See Table 22 5 on page 71 1 0 0 1 x x x x x x x ...

Страница 71: ...0 0 0 0 1 1 1 1 930F EVZ switched to 23V default 1 0 0 1 0 0 1 1 1 1 1 1 0 0 0 0 93F0 EVZ switched to external divider 1 0 0 1 0 0 1 1 1 0 0 1 0 1 1 0 9396 CP OUT switched to high ohmic state default 1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 960F CP OUT switched to low impedance state 1 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 96F0 K1 interface works as ISO9141 or LIN interface depending on ISO LIN bit of initial prog...

Страница 72: ...to UZP 1 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 CA34 Switch 10 VVPERI via AMUX to UZP 1 1 0 0 1 0 1 0 0 0 1 1 1 0 0 0 CA38 Switch VVCORE via AMUX to UZP 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 CA61 Switch VK15 via AMUX to UZP 1 1 0 0 1 0 1 0 0 1 1 0 0 0 1 0 CA62 Switch VK30 via AMUX to UZP 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 CA64 Switch VIREF via AMUX to UZP 1 1 0 0 1 0 1 0 0 1 1 0 1 0 0 0 CA68 Switch VIASG1 via AMUX ...

Страница 73: ...MUX to UZP 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 0 CAE4 1 Table 22 8 IASG Commands Description MSByte LSByte Hex Code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 IASGx switched to 10V mirror factor 10 1 1 1 1 1 0 a b c 0 0 1 1 0 0 1 1 Fx33 IASGx switched to 10V mirror factor 15 1 1 1 1 1 0 a b c 0 0 1 1 1 1 0 0 Fx3C IASGx switched to 5V mirror factor 10 1 1 1 1 1 0 a b c 1 1 0 0 0 0 1 1 FxC3 IASGx switched to 5V mirr...

Страница 74: ...set Low Latch for GKEY function is not set a3 High EVZ switched to 33V EVZ switched to external divider Low EVZ switched to 23V a2 High CP OUT switch is low impedance Low CP OUT switch is high ohmic a1 High CP OUT voltage too low Low CP OUT voltage is in correct voltage range a0 High CP voltage too low Low CP voltage is in correct voltage range b7 High Voltage at pin USP above detection threshold ...

Страница 75: ...bits show the status before reset so that the microcontroller can detect whether or not the ATA6264 is in power up state Table 22 12 Test Command Issued via the MISO line as a Result of the Test Mode Commands Description Command MISO Answer Hex Code Test mode 1 55AA 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 AA55 Test mode 2 AA55 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 55AA Test mode 3 5500 0 0 0 0 0 0 0 1 a b c d e...

Страница 76: ...V to 5V and VK15 3V to 4V In Test mode the watchdog is disabled which means that RESQ and RESQ2 depend on the voltage levels of the pins VCORE VPERI and EVZ In order to provide the programming voltage at VSAT for the ini tial programming VVSAT is set to 11 7V 0 5V in Test mode if the lock bit is not set After a reset Test mode is disabled default The following serial interface commands are used fo...

Страница 77: ...AT COMEVZ FBEVZ VPERIFB VPERI VSAT COMSATI EVZ GNDB OCEVZ GEVZ K30 K15 K15 K1 CP OUT CP K2 RESQ2 UZP RxD2 IASG1 to 5 USP IREF TxD2 RxD1 RESQ GNDD ISENS GNDA TxD1 COMCOO Serial interface Sensor Safety system monitoring D L C net Firing ASIC Enable Enable Firing loops Micro controller COMCOI VCORE SVCORE K1 K30 K2 IASG1 to 5 ...

Страница 78: ...xD1 RxD2 TxD2 RESQ2 VINT MISO RESQ SSQ SCLK SSQ SCLK Cp K30 USP MOSI RxD1 TxD1 RxD2 UZP UZP CP OUT CP OUT IREF GNDB GNDD GNDA K2 IASG3 IASG4 ISENS IASG5 IASG1 K1 TxD2 GEVZ EVZ 33V VPERI 5V VCORE 5V VSAT 9V EVZ FBEVZ COMEVZ K15 COMSATO VPERI VSAT SVCORE VCORE SVSAT SVPERI COMCOO COMCOI COMSATI OCEVZ IASG2 ATA6264 K2 KL30 ...

Страница 79: ...marks ATA6264 ALTW P TQFP44 Tray ATA6264 ALQW P TQFP44 Taped and reeled specifications according to DIN technical drawings 10 0 05 12 0 2 8 12 22 44 34 33 0 2 23 1 11 0 8 Issue 1 11 05 06 Drawing No 6 543 5131 01 4 0 1 0 05 0 6 0 15 1 4 0 05 Dimensions in mm acc JEDEC OUTLINE No MO 112 Package P TQFP 44 0 37 0 07 0 08 ...

Страница 80: ...n History Please note that the following page numbers referred to in this section refer to the specific revision mentioned not to this document Revision No History 4929B AUTO 01 07 Put datasheet in a new template Section 23 Test Mode on page 76 changed ...

Страница 81: ...ramming of the ATA6264 11 5 3 Start up and Power down Procedure 14 5 3 1 Start up Procedure if VVCORE is Programmed to Be 5V or 2 5V 15 5 3 2 The Power down Procedure Takes Place in Different Phases 15 5 3 3 Start up Procedure if VVCORE Programmed to Be 1 88V 16 5 3 4 The Power down Procedure for VVCORE is Programmed to be 1 88V 17 6 Power Supply Sequencing 18 7 Charge Pump 20 8 GKEY Function 22 9...

Страница 82: ...alog Multiplexer for Voltage Measurements 62 20 UZP Buffer 65 21 Chip Temperature Measurement 67 22 Serial Interface Commands 68 22 1 Overview 68 22 2 Set Commands 70 22 3 Serial Interface Status Register 74 23 Test Mode 76 24 Application Circuits 77 25 Ordering Information 79 26 Package Information 79 27 Revision History 80 ...

Страница 83: ...l Operations 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH 1705 Fribourg Switzerland Tel 41 26 426 5555 Fax 41 26 426 5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fax 852 2722 1369 Japan 9F Tonetsu Shinkawa Bldg 1 24 8 S...

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