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6415B–ATARM–03-Oct-08

Application Note

The T

SLCK

min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44

kHz).

– T

RES

= 30 µs

– T3 = 66 µs

– T4 = 352 µs

Figure 4-3.

VDDCORE

and V

VDDIO

Constraints at Power-up

4.2.2

Power-Down Sequence

Switch-off the VDDIOM and VDDIOP power supply prior to or at the same time as VDDCORE.

No power-up or power-down restrictions apply to VDDBU, VDDPLL, VDDANA and VDDUSB.

VDD (V)

Core Supply POR output

VDDIOtyp

Vth+

SLCK

<--Tres ->

VDDCORE

VDDIO

<--------------------- T1--------------------->

<T3>

VDDCOREtyp

Voh

VDDIO > VOH

<------------ T4----------->

0.7V

Содержание AT91 ARM Thumb

Страница 1: ...ingle cycle Access at Maximum Matrix Speed ROM Boot from DataFlash NAND Flash Serial Flash SD Memory Card and EEPROM Ethernet MAC The RX FIFO and TX FIFO Sizes are Increased to 32 Words Hardware ECC Controller Enhancement PDC Channel on TWI controller Selectable Drive to Control the I Os Slew Rate on EBI Signals PIO Controllers All the I O Lines are Schmitt Trigger Inputs Required Power Supplies 0...

Страница 2: ... small current but it is noise sensitive Care must be taken in VDDOSC power supply routing decoupling and also on bypass capacitors Table 4 1 Power Supplies Power supply domain AT91SAM9260 AT91SAM9G20 Range V What is powered Range V What is powered VDDCORE 1 65 1 95 Core 0 9 1 1 Core VDDBU 1 65 1 95 Backup 0 9 1 1 Backup VDDPLL 1 1 65 1 95 PLL and Oscillator 0 9 1 1 PLL VDDOSC 3 N A N A 1 65 3 6 O...

Страница 3: ...evice Prevent the device from booting 4 2 1 Power up Sequence VDDCORE and VDDBU are controlled by internal POR Power on Reset to guarantee that these power sources reach their target values prior to the release of POR VDDIOM and VDDIOP must NOT be powered until VDDCORE has reached a level superior to Vth VDDIOM and VDDIOP must be to 0 7V within TRES T3 after VDDCORE has reached Vth VDDIOM and VDDI...

Страница 4: ... 352 µs Figure 4 3 VVDDCORE and VVDDIO Constraints at Power up 4 2 2 Power Down Sequence Switch off the VDDIOM and VDDIOP power supply prior to or at the same time as VDDCORE No power up or power down restrictions apply to VDDBU VDDPLL VDDANA and VDDUSB VDD V Core Supply POR output VDDIOtyp Vth t SLCK Tres VDDCORE VDDIO T1 T3 VDDCOREtyp Voh VDDIO VOH T4 0 7V ...

Страница 5: ...SAM9260 AT91SAM9G20 Startup time 240 µs 150 µs Table 5 2 Reduced Crystal Table MHz OSCSEL 0 3 0 8 0 18 432 Other Boot on DBGU Yes Yes Yes Yes Boot on USB Yes Yes Yes No Table 5 3 Reduced Crystal Table MHz OSCSEL 0 and Main Oscillator is Bypassed 3 0 8 0 20 0 50 0 Other Boot on DBGU Yes Yes Yes Yes Yes Boot on USB Yes Yes Yes Yes No Table 5 4 Large Crystal Table MHz OSCSEL 1 3 0 3 6864 3 84 4 0 4 9...

Страница 6: ...L 1 and Main Oscillator is Bypassed Table 5 6 PLLA Characteristics PLLA Characteristics AT91SAM9260 AT91SAM9G20 Range 80 240 MHz 400 800 MHz MULA 1 1047 1 254 DIVA 1 255 1 255 Entry frequency 1 32 MHz 2 32 MHz Embedded PLL Filter No Yes Table 5 7 AT91SAM9260 PLLA Frequency Regarding ICPPLLA and OUTA PLL frequency range MHz ICPPLLA OUTA 190 240 1 1 0 80 200 1 0 0 Table 5 8 AT91SAM9G20 PLLA Frequenc...

Страница 7: ...30 100 MHz MULB 1 1047 1 62 DIVB 1 255 1 255 OUTB 01 00 Entry frequency 1 5 MHz 2 32 MHz Embedded PLL Filter Yes Yes Table 5 10 Processor Master Clock Characteristics AT91SAM9260 AT91SAM9G20 Processor Max frequency 180 MHz 400 MHz Bus Max frequency 90 MHz 133 MHz Master clock divider MDIV 1 2 4 1 2 4 6 Processor clock div PDIV N A 1 2 Current consumption on VDDCORE in Active Mode 130 mA 180 90 MHz...

Страница 8: ...nd spectral spreading Trace ringing according to the intrinsic trace characteristics Table 6 1 List of Bus Matrix Masters Master AT91SAM9260 AT91SAM9G20 Master 0 ARM926 Instruction ARM926 Instruction Master 1 ARM926 Data ARM926 Data Master 2 PDC PDC Master 3 USB Host DMA ISI Controller Master 4 ISI Controller Ethernet MAC Master 5 Ethernet MAC USB Host DMA Table 7 1 ECC Controller Connections Devi...

Страница 9: ...d number of bytes Not Fixed Flag Reset is not correct in half duplex mode Not Fixed Oscillators On chip RC startup time Fixed Bad sampling of OSCSEL Fixed SDRAM Controller All SDRAMC Errata Fixed Serial Peripheral Interface SPI Bad Serial Clock Generation on second chip_select when SCBR 1 CPOL 1 and NCPHA 0 Not Fixed Baudrate set to 1 Not Fixed Serial Synchronous Controller SSC Unexpected RK clock...

Страница 10: ...us Asynchronous Receiver Transmitter USART TXD signal is floating in Modem and Hardware Handshaking mode Not Fixed DCD is Active High instead of Low Not Fixed RXBRK flag error in Asynchronous Mode Fixed CTS signal in Hardware Handshake Fixed RTS not expected behavior Fixed Two characters sent if CTS rises during emission Fixed Errata Section Errata Description Status ...

Страница 11: ...B ATARM 03 Oct 08 Application Note Revision History Doc Rev Comments Change Request Ref 6415A First issue 6415B Section 4 1 Power Supply Range updated with VDDPLL constraints See Table 4 1 and Figure 4 1 5790 ...

Страница 12: ...TING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE ...

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