Atmel AT90S2333-8AC Скачать руководство пользователя страница 20 | Manualshive

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AT90S/LS2333 and AT90S/LS4433

20

Notes:

1. Or external power-on reset.

This table shows the start-up times from reset. From sleep, only the clock counting part of the start-up time is used. The
watchdog oscillator is used for timing the real-time part of the start-up time. The number WDT oscillator cycles used for
each time-out is shown in Table 6.

The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section.

Power-On Reset

A Power-On Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is nominally 2.2V. The
POR is activated whenever V

CC

is below the detection level. The POR circuit can be used to trigger the start-up reset, as

well as detect a failure in supply voltage.

The Power-On Reset (POR) circuit ensures that the device is reset from power-on. Reaching the power-on reset threshold
voltage invokes a delay counter, which determines the delay, for which the device is kept in RESET after V

CC

rise. The

time-out period of the delay counter is a combination of internal RC oscillator cycles and external oscillator cycles, and it
can be defined by the user through the CKSEL fuses. The eight different selections for the delay period are presented in
Table 5. The RESET signal is activated again, without any delay, when the V

CC

decreases below detection level.

Figure 25. MCU Start-Up, RESET Tied to VCC.

Table 5. Reset Delay Selections

CKSEL [2:0]

Start-Up Time, t

TOUT

at V

CC

= 2.7V

Start-Up Time, t

TOUT

at V

CC

= 5.0V

Recommended Usage

000

16 ms + 6 CK

4 ms + 6 CK

External Clock, slowly rising power

001

6 CK

6 CK

External Clock, BOD enabled

010

256 ms + 16K CK

64 ms + 16K CK

Crystal Oscillator

011

16 ms + 16K CK

4 ms + 16K CK

Crystal Oscillator, fast rising power

100

16K CK

16K CK

Crystal Oscillator, BOD enabled

101

256 ms + 1K CK

64 ms + 1K CK

Ceramic Resonator

110

16 ms + 1K CK

4 ms + 1K CK

Ceramic Resonator, fast rising power

111

1K CK

1K CK

Ceramic Resonator, BOD enabled

Table 6. Number of Watchdog Oscillator Cycles

Time-out

Number of cycles

4.0 ms (at V

cc

=5.0V)

4K

64 ms (at V

cc

=5.0V)

64K

VCC

RESET

TIME-OUT

INTERNAL

RESET

t

TOUT

V

POT

V

RST

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Содержание AT90S2333-8AC

Страница 1: ...Bytes of In System Programmable EEPROM Endurance 100 000 Write Erase Cycles Programming Lock for Flash Program and EEPROM Data Security Peripheral Features One 8 bit Timer Counter with Separate Presca...

Страница 2: ...le Watchdog Timer with internal oscillator an SPI serial port and two software selectable power saving modes The Idle mode stops the CPU while allowing the SRAM timer counters SPI port and interrupt s...

Страница 3: ...GISTER TIMER COUNTERS INSTRUCTION DECODER DATA DIR REG PORTB DATA DIR REG PORTC DATA REGISTER PORTB DATA REGISTER PORTC ANALOG MUX ADC DATA REGISTER PORTD PROGRAMMING LOGIC TIMING AND CONTROL OSCILLAT...

Страница 4: ...nal pull up resistors The Port D output buffers can sink 20 mA As inputs Port D pins that are externally pulled low will source current if the pull up resistors are activated Port D also serves the fu...

Страница 5: ...ock If the oscillator is to be used as a clock for an external device the clock signal from XTAL2 may be routed to one HC buffer while reducing the load capacitor by 5 pF as shown in Figure 3 To drive...

Страница 6: ...metic and logic functions between registers or between a constant and a register Single register operations are also executed in the ALU Figure 5 shows the AT90S2333 4433 AVR RISC microcontroller arch...

Страница 7: ...on the stack The stack is effec tively allocated in the general data SRAM and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM All user programs must initi...

Страница 8: ...user Data Space Although not being physically implemented as SRAM locations this memory organization provides great flexibility in access of the registers as the X Y and Z registers can be set to inde...

Страница 9: ...SRAM Organization SRAM Data Memory The figure above shows how the AT90S2333 4433 SRAM Memory is organized The lower 224 Data Memory locations address the Register file the I O Memory and the internal...

Страница 10: ...s for access to the Flash program memory SRAM Register File and I O data memory This section describes the different addressing modes sup ported by the AVR architecture In the figures OP means the ope...

Страница 11: ...bit Data Address is contained in the 16 LSBs of a two word instruction Rd Rr specify the destination or source register Data Indirect with Displacement Figure 14 Data Indirect with Displacement Operan...

Страница 12: ...nted before the operation Operand address is the decremented contents of the X Y or the Z register Data Indirect with Post Increment Figure 17 Data Indirect Addressing with Post Increment The X Y or t...

Страница 13: ...set LSB 1 Indirect Program Addressing IJMP and ICALL Figure 19 Indirect Program Memory Addressing Program execution continues at address contained by the Z register i e the PC is loaded with the conte...

Страница 14: ...d from the external clock crystal for the chip No internal clock division is used Figure 21 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and th...

Страница 15: ...ol Register 32 52 TCNT0 Timer Counter0 8 bit 2F 4F TCCR1A Timer Counter1 Control Register A 2E 4E TCCR1B Timer Counter1 Control Register B 2D 4D TCNT1H Timer Counter1 High Byte 2C 4C TCNT1L Timer Coun...

Страница 16: ...ever be written Some of the status flags are cleared by writing a logical one to them Note that the CBI and SBI instructions will operate on all bits in the I O register writing a one back into any fl...

Страница 17: ...ve Flag The negative flag N indicates a negative result from an arithmetical or logical operation See the Instruction Set Description for detailed information Bit 1 Z Zero Flag The zero flag Z indicat...

Страница 18: ...p RESET Reset Handler 001 rjmp EXT_INT0 IRQ0 Handler 002 rjmp EXT_INT1 IRQ1 Handler 003 rjmp TIM1_CAPT Timer1 Capture Handler 004 rjmp TIM1_COMP Timer1 compare Handler 005 rjmp TIM1_OVF Timer1 Overflo...

Страница 19: ...jump instruction to the reset handling routine If the pro gram never enables an interrupt source the interrupt vectors are not used and regular program code can be placed at these locations The circui...

Страница 20: ...is kept in RESET after VCC rise The time out period of the delay counter is a combination of internal RC oscillator cycles and external oscillator cycles and it can be defined by the user through the...

Страница 21: ...ith a 47 nF to 100 nF capacitor if the BOD function is used The BOD circuit can be enabled disabled by the fuse BODEN When BODEN is enabled BODEN programmed and VCC decreases to a value below the trig...

Страница 22: ...s zero Bit 3 WDRF Watchdog Reset Flag This bit is set if a watchdog reset occurs The bit is cleared by a power on reset or by writing a logic zero to the flag Bit 2 BORF Brown Out Reset Flag This bit...

Страница 23: ...pt routine and restored when returning from an interrupt routine This must be handled by software General Interrupt Mask Register GIMSK Bit 7 INT1 External Interrupt Request 1 Enable When the INT1 bit...

Страница 24: ...en the OCIE1 bit is set one and the I bit in the Status Register is set one the Timer Counter1 Compare Match inter rupt is enabled The corresponding interrupt at vector 004 is executed if a Compare ma...

Страница 25: ...tively TOV0 is cleared by writing a logic one to the flag When the SREG I bit and TOIE0 Timer Counter0 Overflow Interrupt Enable and TOV0 are set one the Timer Counter0 Overflow interrupt is executed...

Страница 26: ...ing edges If edge or toggle interrupt is selected pulses that last longer than one clock period will generate an interrupt Shorter pulses are not guaranteed to generate an interrupt If low level inter...

Страница 27: ...interrupt and watchdog reset If wake up from the Analog Comparator interrupt is not required the analog comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Stat...

Страница 28: ...as described in the specification for the Timer Counter0 Control Register TCCR0 The overflow status flag is found in the Timer Counter Interrupt Flag Register TIFR Control signals are found in the Tim...

Страница 29: ...ed CK modes are scaled directly from the CK oscillator clock If the external pin modes are used for Timer Counter0 transitions on PD4 T0 will clock the counter even if the pin is configured as an outp...

Страница 30: ...agram The 16 bit Timer Counter1 can select clock source from CK prescaled CK or an external pin In addition it can be stopped as described in the specification for the Timer Counter1 Control Register...

Страница 31: ...ts to the Input Capture Reg ister ICR1 triggered by an external event on the Input Capture Pin ICP The actual capture event settings are defined by the Timer Counter1 Control Register TCCR1 In additio...

Страница 32: ...he rising edge of the input capture pin ICP Bits 5 4 Res Reserved bits These bits are reserved bits in the AT90S2333 4433 and always read zero Bit 3 CTC1 Clear Timer Counter1 on Compare match When the...

Страница 33: ...this byte of data is combined with the byte data in the TEMP register and all 16 bits are written to the TCNT1 Timer Counter1 register simultaneously Consequently the high byte TCNT1H must be accesse...

Страница 34: ...input capture flag ICF1 is set one Since the Input Capture Register ICR1 is a 16 bit register a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously When...

Страница 35: ...ch operation a read from OCR1 will read the contents of the temporary loca tion This means that the most recently written value always will read out of OCR1 When OCR1 contains 0000 or TOP the output O...

Страница 36: ...Watchdog reset the AT90S2333 4433 resets and executes from the reset vector For timing details on the Watchdog reset refer to page 22 To prevent unintentional disabling of the watchdog a special turn...

Страница 37: ...er is enabled The different prescaling values and their corresponding time out Periods are shown inTable 16 Note The frequency of the watchdog oscillator is voltage dependent as shown in the Electrica...

Страница 38: ...ration the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register For the EEPROM read operation the EEDR contains the data read out from the EEPROM at th...

Страница 39: ...requested data is found in the EEDR register The EEPROM read access takes one instruction and there is no need to poll the EERE bit When EERE has been set the CPU is halted for four cycles before the...

Страница 40: ...n the master mode and is the clock input in the slave mode Writing to the SPI data register of the master CPU starts the SPI clock generator and the data written shifts out of the PB3 MOSI pin and int...

Страница 41: ...a slave and starting to send data to it To avoid bus contention the SPI system takes the following actions 1 The MSTR bit in SPCR is cleared and the SPI system becomes a slave As a result of the SPI...

Страница 42: ...Der When the DORD bit is set one the LSB of the data word is transmitted first When the DORD bit is cleared zero the MSB of the data word is transmitted first Bit 4 MSTR Master Slave Select This bit s...

Страница 43: ...I data register SPDR is written during a data transfer The WCOL bit and the SPIF bit are cleared zero by first reading the SPI Status Register with WCOL set one and then accessing the SPI Data Registe...

Страница 44: ...Start Bit detection Three separate interrupts on TX Complete TX Data Register Empty and RX Complete Multi Processor Communication Mode Data Transmission A block schematic of the UART transmitter is sh...

Страница 45: ...register On the Baud Rate clock following the transfer operation to the shift register the start bit is shifted out on the TXD pin Then follows the data LSB first When the stop bit has been shifted o...

Страница 46: ...been lost The OR bit is buffered and is updated when the valid data byte in UDR is read Thus the user should always check the OR bit after reading the UDR register in order to detect any overruns if...

Страница 47: ...set one when the entire character including the stop bit in the Transmit Shift register has been shifted out and no new data has been written to UDR This flag is especially useful in half duplex commu...

Страница 48: ...When this bit is set one a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine to be executed provided that global interrupts are enabled Bit 4 RXEN Receiver Enab...

Страница 49: ...0 0 U B R 0 7 8 B a u d R a te 3 2 7 6 8 M H z E rro r 3 6 8 6 4 M H z E rro r 4 M H z E rro r 2 4 0 0 U B R 8 4 0 4 U B R 9 5 0 0 U B R 1 0 3 0 2 4 8 0 0 U B R 4 2 0 8 U B R 4 7 0 0 U B R 5 1 0 2 9...

Страница 50: ...rator The user can select Inter rupt triggering on comparator output rise fall or toggle A block diagram of the comparator and its surrounding logic is shown in Figure 43 Figure 43 Analog Comparator B...

Страница 51: ...bit enables the Input Capture function in Timer Counter1 to be triggered by the analog comparator The comparator output is in this case directly connected to the Input Capture front end logic making t...

Страница 52: ...the volt age on AVCC must not differ more than 0 3 V from VCC See the paragraph ADC Noise Canceling Techniques on how to connect these pins An external reference voltage must be applied to the AREF pi...

Страница 53: ...to the data registers is prohibited between reading of ADCH and ADCL the interrupt will trigger even if the result gets lost Prescaling Figure 45 ADC Prescaler The ADC contains a prescaler which divi...

Страница 54: ...Conversion Free Run 14 25 25 125 500 1st Conversion Single 14 25 26 130 520 Free Run Conversion 2 13 13 65 260 Single Conversion 2 13 14 70 280 MSB of result LSB of result ADC clock ADSC Hold strobe...

Страница 55: ...tine ADC Multiplexer Select Register ADMUX Bit 7 Res Reserved Bits These bits are reserved bits in the AT90S2333 4433 and should be written to zero if accessed Bit 6 ADCBG ADC Bandgap Select When this...

Страница 56: ...pletes Writing a 0 to this bit has no effect Bit 5 ADFR ADC Free Run Select When this bit is set one the ADC operates in Free Run Mode In this mode the ADC samples and updates the data regis ters cont...

Страница 57: ...e the AT90S2333 4433 generates EMI which might affect the accuracy of analog measure ments If conversion accuracy is critical the noise level can be reduced by applying the following techniques 1 The...

Страница 58: ...ck 200 kHz 1 2 LSB Absolute accuracy VREF 4V ADC clock 1 MHz 4 LSB Absolute accuracy VREF 4V ADC clock 2 MHz 16 LSB Integral Non Linearity VREF 2V 0 5 LSB Differential Non Linearity VREF 2V 0 5 LSB Ze...

Страница 59: ...inputs and are externally pulled low they will source current if the internal pull up resistors are activated The Port B pins with alternate functions are shown in the following table When the pins a...

Страница 60: ...n of this pin is controlled by DDB4 When the pin is forced to be an input the pull up can still be controlled by the PORTB4 bit See the description of the SPI port for further details MOSI Port B Bit...

Страница 61: ...T RESET C C WD WP RD MOS PULL UP PB0 R R WP WD RL RP RD ACIC ACO WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB COMPARATOR IC ENABLE COMPARATOR OUTPUT DDB6 PORTB0 NOISE CANCELER EDGE...

Страница 62: ...SS MSTR SPE WP WD RL RP RD MSTR SPE WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI MASTER ENABLE SPI ENABLE DDB2 PORTB2 RL RP DATA BUS D D Q Q RESET RESET C C WD WP RD MOS PULL...

Страница 63: ...RP RD SPE MSTR WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB SPI ENABLE MASTER SELECT DDB4 PORTB4 SPE MSTR SPI SLAVE OUT SPI MASTER IN RL RP DATA BUS D D Q Q RESET RESET C C WD WP R...

Страница 64: ...rection Register DDRC Port C Input Pins Address PINC The Port C Input Pins address PINC is not a register and this address enables access to the physical value on each Port C pin When reading PORTC th...

Страница 65: ...ile the Data Register and the Data Direction Register are read write The Port D output buffers can sink 20 mA As inputs Port D pins that are externally pulled low will source current if the pull up re...

Страница 66: ...has to be configured as an output pin The port pins are tristated when a reset condition becomes active even if the clock is not running Table 26 Port D Pins Alternate Functions Port Pin Alternate Fun...

Страница 67: ...rt D Bit 5 T1 Timer Counter1 counter source See the timer description for further details T0 Port D Bit 4 T0 Timer Counter0 counter source See the timer description for further details INT1 Port D Bit...

Страница 68: ...in PD1 DATA BUS D D Q Q RESET RESET C C WD WP RD MOS PULL UP PD0 RXD RXEN WP WD RL RP RD RXD RXEN WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART RECEIVE DATA UART RECEIVE ENABLE...

Страница 69: ...0S LS4433 69 Figure 59 Port D Schematic Diagram Pins PD2 and PD3 Figure 60 Port D Schematic Diagram Pins PD4 and PD5 WP WD RL RP RD n WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 4...

Страница 70: ...Schematic Diagram Pins PD6 and PD7 DATA BUS D D Q Q RESET RESET C C WD WP RD MOS PULL UP PDn AINm TO COMPARATOR WP WD RL RP RD n m WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 6 7...

Страница 71: ...e three bytes reside in a separate address space For the AT90S4433 1 they are 1 000 1E indicates manufactured by Atmel 2 001 92 indicates 4KB Flash memory 3 002 03 indicates AT90S4433 device when sign...

Страница 72: ...ames describing their function during parallel programming See Figure 62 and Table 30 Pins not described in Table 30 are referenced by pin names The XA1 XA0 pins determine the action executed when the...

Страница 73: ...ame Mapping Signal Name in Programming Mode Pin Name I O Function RDY BSY PD1 O 0 Device is busy programming 1 Device is ready for new command OE PD2 I Output Enable Active low WR PD3 I Write Pulse Ac...

Страница 74: ...3 Set DATA Address low byte 00 FF 4 Give XTAL1 a positive pulse This loads the address low byte D Load Data Low Byte 1 Set XA1 XA0 to 01 This enables data loading 2 Set DATA Data low byte 00 FF 3 Giv...

Страница 75: ...64 Programming the Flash Waveforms continued Reading the Flash The algorithm for reading the Flash memory is as follows refer to Programming the Flash for details on Command and Address loading 1 A L...

Страница 76: ...5 SPIEN Fuse bit Bit 4 BODLEVEL Fuse bit Bit 3 BODEN Fuse bit Bit 2 CKSEL2 Fuse bit Bit 1 CKSEL1 Fuse bit Bit 0 CKSEL0 Fuse bit Bit 7 6 1 These bits are reserved and should be left unprogrammed 1 3 G...

Страница 77: ...Signature Bytes The algorithm for reading the Signature bytes is as follows refer to Programming the Flash for details on Command and Address loading 1 A Load Command 0000 1000 2 C Load Address Low By...

Страница 78: ...5V 10 Symbol Parameter Min Typ Max Units VPP Programming Enable Voltage 11 5 12 5 V IPP Programming Enable Current 250 tDVXH Data and Control Setup before XTAL1 High 67 ns tXHXL XTAL1 Pulse Width High...

Страница 79: ...two XTAL1 cycles duration after SCK has been set to 0 2 Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI PB3 3 The serial programm...

Страница 80: ...e meant to contain FF can be skipped This does not apply if the EEPROM is reprogrammed without first chip erasing the device Data Polling Flash When a byte is being programmed into the Flash reading t...

Страница 81: ...oo Read H high or low data o from Program memory at word address a b Write Program Memory 0100 H000 xxxx xaaa bbbb bbbb iiii iiii Write H high or low data i to Program memory at word address a b Read...

Страница 82: ...equency VCC 4 0 6 0V 0 8 MHz tCLCL Oscillator Period VCC 4 0 6 0V 125 ns tSHSL SCK Pulse Width High 2 tCLCL ns tSLSH SCK Pulse Width Low 2 tCLCL ns tOVSH MOSI Setup to SCK High tCLCL ns tSHOX MOSI Hol...

Страница 83: ...ns 300 0 mA DC Characteristics TA 40 C to 85 C VCC 2 7V to 6 0V unless otherwise noted Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage Except XTAL RESET 0 5 0 3VCC 1 V VIL1 Input Lo...

Страница 84: ...the listed test condition 4 Although each I O port can source more than the test conditions 3mA at Vcc 5V 1 5mA at Vcc 3V under steady state conditions non transient the following must be observed 1 T...

Страница 85: ...Table 39 External Clock Drive Symbol Parameter VCC 2 7V to 6 0V VCC 4 0V to 6 0V Units Min Max Min Max 1 tCLCL Oscillator Frequency 0 4 0 8 MHz tCLCL Clock Period 250 125 ns tCHCX High Time 100 50 ns...

Страница 86: ...d for one pin as CL VCC f where CL load capacitance VCC operating voltage and f average switching frequency of I O pin The parts are characterized at frequencies higher than test limits Parts are not...

Страница 87: ...4 6 8 10 12 14 2 2 5 3 3 5 4 4 5 5 5 5 6 ACTIVE SUPPLY CURRENT vs Vcc FREQUENCY 4 MHz I cc mA Vcc V T 25 C A T 85 C A 0 2 4 6 8 10 12 14 16 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Vcc 6V Vcc 5 5V Vcc...

Страница 88: ...own Supply Current vs VCC T 25 C A T 85 C A IDLE SUPPLY CURRENT vs Vcc I cc mA Vcc V FREQUENCY 4 MHz 0 1 2 3 4 5 6 2 2 5 3 3 5 4 4 5 5 5 5 6 0 5 10 15 20 25 2 2 5 3 3 5 4 4 5 5 5 5 6 T 85 C A T 25 C A...

Страница 89: ...Supply Current vs VCC 0 20 40 60 80 100 120 2 2 5 3 3 5 4 4 5 5 5 5 6 POWER DOWN SUPPLY CURRENT vs Vcc I cc Vcc V WATCHDOG TIMER ENABLED T 85 C A T 25 C A 0 20 40 60 80 100 120 140 2 2 5 3 3 5 4 4 5...

Страница 90: ...Comparator Offset Voltage vs Common Mode Voltage ANALOG COMPARATOR CURRENT vs Vcc I cc mA Vcc V T 25 C A T 85 C A 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 2 2 5 3 3 5 4 4 5 5 5 5 6 0 2 4 6 8 10 12 14 16...

Страница 91: ...tor Input Leakage Current 0 2 4 6 8 10 0 0 5 1 1 5 2 2 5 3 ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE Common Mode Voltage V Offset Voltage mV V 2 7V cc T 85 C A T 25 C A 60 50 40 30 20 10...

Страница 92: ...S2333 and AT90S LS4433 92 Figure 81 Watchdog Oscillator Frequency vs VCC 0 200 400 600 800 1000 1200 1400 1600 2 2 5 3 3 5 4 4 5 5 5 5 6 T 85 C A T 25 C A WATCHDOG OSCILLATOR FREQUENCY vs Vcc V V cc F...

Страница 93: ...Current vs Input Voltage Figure 83 Pull Up Resistor Current vs Input Voltage 0 20 40 60 80 100 120 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 PULL UP RESISTOR CURRENT vs INPUT VOLTAGE V 5V cc I A OP V V OP T 85...

Страница 94: ...Source Current vs Output Voltage 0 10 20 30 40 50 60 70 80 0 0 5 1 1 5 2 2 5 3 V 5V cc I mA OL V V OL T 85 C A T 25 C A I O PIN SINK CURRENT vs OUTPUT VOLTAGE 0 2 4 6 8 10 12 14 16 18 0 0 5 1 1 5 2 2...

Страница 95: ...igure 87 I O Pin Source Current vs Output Voltage 0 5 10 15 20 25 30 0 0 5 1 1 5 2 I mA OL V V OL T 85 C A T 25 C A I O PIN SINK CURRENT vs OUTPUT VOLTAGE V 2 7V cc 0 1 2 3 4 5 6 0 0 5 1 1 5 2 2 5 3 I...

Страница 96: ...vs VCC Figure 89 I O Pin Input Hysteresis vs VCC 0 0 5 1 1 5 2 2 5 2 7 4 0 5 0 Threshold Voltage V Vcc I O PIN INPUT THRESHOLD VOLTAGE vs Vcc T 25 C A 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 2...

Страница 97: ...ved 21 41 WDTCR WDTOE WDE WDP2 WDP1 WDP0 page 36 20 40 Reserved 1F 3F Reserved 1E 3E EEAR EEPROM Address Register page 38 1D 3D EEDR EEPROM Data Register page 38 1C 3C EECR EERIE EEMWE EEWE EERE page...

Страница 98: ...flags are cleared by writing a logical one to them Note that the CBI and SBI instructions will operate on all bits in the I O register writing a one back into any flag read as set thus clearing the f...

Страница 99: ...al if Rd Rr PC PC 2 or 3 None 1 2 3 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry Rd Rr C Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit...

Страница 100: ...Rd P None 1 OUT P Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 BIT AND BIT TEST INSTRUCTIONS SBI P b Set Bit in I O Register I...

Страница 101: ...28P3 Commercial 0 C to 70 C AT90S2333 8AI AT90S2333 8PI 32A 28P3 Industrial 40 C to 85 C 2 7 6 0V 4 AT90LS4433 4AC AT90LS4433 4PC 32A 28P3 Commercial 0 C to 70 C AT90LS4433 4AI AT90LS4433 4PI 32A 28P...

Страница 102: ...ID 0 80 0 031 BSC 7 00 0 276 BSC 0 7 0 20 0 008 0 10 0 004 0 75 0 030 0 45 0 018 1 20 0 047 MAX 0 15 0 006 0 05 0 002 28P3 28 lead 0 300 Wide Plastic Dual Inline Package PDIP Dimensions in Inches and...

Страница 103: ...arters 2325 Orchard Parkway San Jose CA 95131 TEL 408 441 0311 FAX 408 487 2600 Europe Atmel U K Ltd Coliseum Business Centre Riverside Way Camberley Surrey GU15 3YL England TEL 44 1276 686 677 FAX 44...

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