Astronics OMNIBUS II NI PXIe, Руководство пользователя

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OMNIBUS II FEATURES
4-2 OmniBus II NI PXIe User Manual
4.2.3 Continuous Built-in Test (CBIT)
During card operation, dedicated hardware constantly monitors multiple internal
modules for errors. These sources include error detection/correction circuits for
system memory and FPGA, protocol specific tests, and the system monitor (see
Figure 4.1). You can access the status of these tests through the API via polling or
interrupts.
The system monitor polls temperature data from sensors located on the card. You
can read present values, as well as historic minimum and maximum values, from
the card. The API allows for setting of user temperature limits and enabling noti-
fication of exceeded limits. The OB2 will halt card operation, to protect the system,
if the temperature-sensor measurements exceed built-in system limits.
Figure 4.1—Built-in Test and System Monitor Architecture
4.3 System Time Synchronization
Systems with high reliability and fidelity requirements need system-level time
synchronization to reduce the effort involved to compare event timing across
interconnected devices. The OB2 series family introduces the Timing
Synchronization Manager (TSM) to provide the ability to synchronize time
between an external reference (IRIG PCM, IRIG AM, PPS) and the protocol cores
on the OB2. Additionally, using one of the above references or a 10 MHz input,
the TSM can adjust the frequency of the local clock oscillator up to 425 ppm to
reduce clock drift between the OB2 and the external reference. Use of the drift
control functionality can help increase synchronization between the OB2 core
timer and the external reference during the gap between timing samples.