ASROCK Rack WC621D8A-2T, Руководство пользователя

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WC621D8A-2T
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DRAM Configuration
Enforce POR
Enable to enforce POR restrictions for DDR4 frequency and voltage programming.
IMC BCLK
If [Auto] is selected, it will be 100MHz or 133MHz.
Primary Timing
tCL
The time between sending a column address to the memory and the beginning of the data
in response.
tRCD
The number of clock cycles required between the opening of a row of memory and
accessing columns within it.
tRP
The number of clock cycles required between the issuing of the precharge command
and opening the next row.
tRAS
The number of clock cycles required between a bank active command and issuing the
precharge command.
CR
The delay between when a memory chip is selected and when the first active command can
be issued.
Secondary Timing
tWR
The amount of delay that must elapse after the completion of a valid write operation,
before an active bank can be precharged.
tRFC
The number of clocks from a Refresh command until the first Activate command to