Artesyn PmPPC440, Руководство пользователя

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On-Card Memory 3-5
10003794-05
3.3.2 SDRAM
The PmPPC440 supports 16, 128, 256, and 512 megabytes of 72-bit wide synchro-
nous dynamic random access memory (SDRAM). The PmPPC440 also will sup-
port one gigabyte of SDRAM (when the 1-gigabyte devices become available). The
SDRAM interface implements eight additional bits to allow for error correcting
code (ECC).
The SDRAM is in the form of a small-outline, dual in-line memory module (SO-
DIMM) device. A serial EEPROM on the SO-DIMM provides configuration infor-
mation, accessible via the I
2
C interface at address A2
16
. The SDRAM occupies
physical addresses from 0000,0000
16
to 7FFF,FFFF
16
on the Processor Local Bus
(PLB). The PPC440GP processor controls the SDRAM and supports a double data
rate (DDR) interface that allows for transfer speeds of up to 266MHz.
3.3.3 EEPROMs
The PPC440GP uses a two-kilobit read-only serial EEPROM at hex location A0
16
on the I
2
C bus to store PPC440GP configuration data. If the configuration data
becomes corrupted, the processor may hang after reset. To reduce the risk of cor-
ruption, the Configuration Write-Protect register at C100,0030
16
controls access
to the write-protect (WP) pin of the EEPROM. For bit zero: 1 = write-protected
(default), 0 = not write-protected.
The PmPPC440 also has a 64-kilobit serial EEPROM at hex location A8
16
on the
I
2
C bus to provide additional non-volatile memory space.
Figure 3-3. Memory Map for 64-Kilobit EEPROM
3 2 1 0
reserved WP
Register Map 3-1. Configuration Write-Protect
Environment Variables
0A00
0000
Artesyn Reserved
0F00
Operating System Reserved
1000
User Space
2000