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System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
193
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External Register Set on page 226
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Chip Configuration on page 226
3.2.1 SDRAM Accesses
The section discusses the following topics:
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Four-beat Reads/Writes on page 193
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Single-beat Reads/Writes on page 193
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Address Pipelining on page 193
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Page Holding on page 194
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SDRAM Speeds on page 194
3.2.1.1 Four-beat Reads/Writes
The SMC performs best when doing bursting (4-beat accesses). This is made possible by the
burst nature of synchronous DRAMs. When the PPC60x Master begins a burst read to SDRAM,
the SMC starts the access and when the access time is reached, the SDRAM provides all four
beats of data, one on each clock. Hence, the SMC can provide the four beats of data with zero
idle clocks between each beat.
3.2.1.2 Single-beat Reads/Writes
Because of start-up, addressing, and completion overhead, single-beat accesses to and from
the PPC60x bus do not achieve data rates as high as do four-beat accesses. Single-beat writes
are the slowest because they require that the SMC perform a read cycle then a write cycle to
the SDRAM in order to complete. Fortunately, in most PPC60x systems, single-beat accesses
can be held to a minimum, especially with data cache and copyback modes in place.
3.2.1.3 Address Pipelining
The SMC takes advantage of the fact that PPC60x processors can do address pipelining. Many
times while a data cycle is finishing, the PPC60x processor begins a new address cycle. The SMC
can begin the next SDRAM access earlier when this happens, thus increasing throughput.