ARM ARM966E-S, Техническое справочное руководство

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AC Parameters
B-12 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A
B.2 AC timing parameter definitions
Table B-1 shows target AC parameters. All figures are expressed as percentages of the
CLK period at maximum operating frequency.
Note
The figures quoted are relative to the rising clock edge after the clock skew for internal
buffering has been added. Inputs given a 0% hold figure therefore require a positive hold
relative to the top- level clock input. The amount of hold required is equivalent to the
internal clock skew.
Table B-1 AC parameters
Symbol Parameter Min Max
T
cyc
CLK cycle time 100% -
T
ishen
HCLKEN input setup time to rising CLK 85% -
T
ihhen
HCLKEN input hold time from rising CLK - 0%
T
isrst
HRESETn deassertion input setup time to rising CLK 90% -
T
ihrst
HRESETn deassertion input hold time from rising CLK - 0%
T
ovreq
Rising CLK to HBUSREQ valid - 30%
T
ohreq
HBUSREQ hold time from rising CLK >0% -
T
ovlck
Rising CLK to HLOCK valid - 30%
T
ohlck
HLOCK hold time from rising CLK >0% -
T
isgnt
HGRANT input setup time to rising CLK 40% -
T
ihgnt
HGRANT input hold time from rising CLK - 0%
T
ovtr
Rising CLK to HTRANS[1:0] valid - 30%
T
ohtr
HTRANS[1:0] hold time from rising CLK >0% -
T
ova
Rising CLK to HADDR[31:0] valid - 30%
T
oha
HADDR[31:0] hold time from rising CLK >0% -
T
ovct
l Rising CLK to AHB control signals valid - 30%
T
ohctl
AHB control signals hold time from rising CLK >0% -