VIPER
Power and power management
Processor power management
The power manager in the PXA255 offers the ability to disable the clocks to the different
internal peripherals. By default, all clocks are enabled after reset. To reduce power
consumption disable the clocks for any unused peripherals.
The clock speed of the processor core, PXbus (the internal bus connecting the
microprocessor core and the other blocks of the PXA255), LCD and SDRAM can also
be changed to achieve a balance between performance and power consumption. For
more details on the internal power manager please see the Intel PXA255 developer’s
manual on the Development Kit CD.
To adjust the core voltage, write the values shown in the following table to the LTC1659
DAC. Please see the LTC1659 datasheet and Intel
®
PXA255 Processor Electrical,
Mechanical, and Thermal Specification on the Development Kit CD.
DAC Data Hex Value
CPU Core Voltage Comment
0x000
1.65V
Not recommended to set the VCORE above
1.3V as the power consumption will increase
for no performance benefit.
0x325
1.29V
Typical VCORE for peak voltage range at
400MHz operation.
Maximum VCORE for medium voltage range
at 200MHz operation.
0xDE5
1.1V
Typical VCORE for high voltage range at
300MHz operation.
0xFFF
1.06V
Typical VCORE for low voltage and medium
voltage range, suitable for 100MHz to
200MHz operation.
When the microprocessor is in sleep mode, the CPU core voltage is shutdown.
To communicate with the VCORE DAC, use the following pins to emulate the LTC1659
interface:
GPIO
LTC1659 DAC pin Function
GPIO6 Data
GPIO11
Clock
GPIO19 Chip
Select
© 2004 Arcom Issue H
55
