registers within the 386EX processor (see memory and I/O maps in
Section 4. Using the TARGET386EX).
There are eight interrupt request lines on the STEbus, ATNRQ7* to
ATNRQ0*. These are usually driven by slave boards to request
action from a master. STEbus interrupt lines are level triggered and
slave boards may share interrupt lines. The TARGET386EX
monitors ATNRQ3*, ATNRQ2*, ATNRQ1* and ATNRQ0*. The
Target386EX may also generate an interrupt on any of these four
lines to the STEbus in either default master, potential master or slave
mode.
All transfers on the STEbus are monitored by bus timeout circuit
that terminates any cycles that are longer than 8us or 4us (link
selectable). This is required because if no slave board responds to an
STEbus cycle then the bus could stay in that bus cycle indefinitely,
the bus timeout monitor prevents this. Bus timeouts on the
TARGET386EX can optionally (link) generate an interrupt to the
386EX processor to indicate that a transfer problem took place.
PC/104 and the TARGET386EX
PC/104 is a small form factor version of the PC/AT ISA bus (IEEE
P996 draft standard) designed for embedded applications. The
TARGET386EX is a PC/104 16/8 bit master controller. It allows 16
and 8 bit cycles with dynamic bus sizing (16 bit transfers to 8 bit
boards are automatically split into two 8 bit transfers) for both
memory and I/O PC/104 peripherals. The TARGET386EX PC/104
interface allows PC/104 expansion boards to extend bus transfers
using the IOCHRDY signal and to shorten the default cycle length
using ENDXFR*.
The TARGET386EX PC/104 interface supports a subset of the
PC/AT interrupts. These are edge triggered.
The TARGET386EX PC/104 interface does not support PC/104
DMA or MASTER* cycles.
There is a PC/104 bus timeout monitor that terminates bus cycles
that have been extended to greater than 16us by IOCHRDY.
STEbus and PC/104 interaction on the TARGET386EX
The TARGET386EX can direct expansion bus accesses to either the
STEbus or the PC/104 bus. At power-up the PC/104 bus is defined
as the default bus and the board is reset to be an STEbus slave. All
accesses to addresses not covered by one of the 386EX chip select
ranges (see Section 4. Using the TARGET386EX) is directed out onto
the PC/104 bus. The DEFSTE bit in on-board General Control
Register 1 changes the default expansion bus to STEbus (note that
bits 0 and 1 of this register must also be changed to configure the
board as an STEbus master before STEbus accesses can occur). Four
of the 386EX chip select lines are left free for application software to
J539 TARGET386EX
2192-08270-000-000
Appendix C. Reference
Page 36
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