Frequently Asked Questions
A-3
Q: What is Bus Master IDE (DMA mode)?
A: The traditional PIO (Programmable I/O) IDE requires the CPU to involve in all
the activities of the IDE access including waiting for the mechanical events.
To reduce the workload of the CPU, the bus master IDE device transfers data
from/to memory without interrupting CPU, and releases CPU to operate
concurrently while data is transferring between memory and IDE device. You
need the bus master IDE driver and the bus master IDE HDD to support bus
master IDE mode. Note that it is different with master/slave mode of the IDE
device connection. For more details, refer to section 2.3 "Connectors".
Q: What is the Ultra DMA/33?
A: This is the new specification to improve IDE HDD data transfer rate. Unlike
traditional PIO mode, which only uses the rising edge of IDE command signal
to transfer data, the DMA/33 uses both rising edge and falling edge. Hence,
the data transfer rate is double of the PIO mode 4 or DMA mode 2. (16.6MB/s
x2 = 33MB/s).
The following table lists the transfer rate of IDE PIO and DMA modes. The
IDE bus is 16-bit, which means every transfer is two bytes.
Mode
Clock per
33MHz
PCI
Clock
count
Cycle
time
Data Transfer rate
PIO mode 0
30ns
20
600ns
(1/600ns) x 2byte = 3.3MB/s
PIO mode 1
30ns
13
383ns
(1/383ns) x 2byte = 5.2MB/s
PIO mode 2
30ns
8
240ns
(1/240ns) x 2byte = 8.3MB/s
PIO mode 3
30ns
6
180ns
(1/180ns) x 2byte = 11.1MB/s
PIO mode 4
30ns
4
120ns
(1/120ns) x 2byte = 16.6MB/s
DMA mode 0
30ns
16
480ns
(1/480ns) x 2byte = 4.16MB/s
DMA mode 1
30ns
5
150ns
(1/150ns) x 2byte = 13.3MB/s
DMA mode 2
30ns
4
120ns
(1/120ns) x 2byte = 16.6MB/s
DMA/33
30ns
4
120ns
(1/120ns) x 2byte x2 = 33MB/s
Q: What is ACPI (Advanced Configuration & Power Interface) and OnNow?
A: The ACPI is new power management specification of 1997 (PC97). It intends
to save more power by taking full control of power management to operating
system and not through BIOS. Because of this, the chipset or super I/O chip
needs to provide standard register interface to OS (such as Win97) and
provides the ability for OS to shutdown and resume power of different part of
chip. The idea is a bit similar to the PnP register interface.
