92
M
M
X
X
4
4
L
L
R
R
-
-
G
G
N
N
/
/
M
M
X
X
4
4
G
G
V
V
R
R
-
-
G
G
N
N
O
O
n
n
l
l
i
i
n
n
e
e
M
M
a
a
n
n
u
u
a
a
l
l
S
S
D
D
R
R
A
A
M
M
(
(
S
S
y
y
n
n
c
c
h
h
r
r
o
o
n
n
o
o
u
u
s
s
D
D
R
R
A
A
M
M
)
)
SDRAM is one of the DRAM technologies that allow DRAM to use the same clock as the CPU host bus (EDO and FPM are
asynchronous and do not have clock signal). It is similar as PBSRAM to use burst mode transfer. SDRAM comes in 64-bit
168-pin DIMM and operates at 3.3V, and have been gradually replaced by DDR RAM.
S
S
A
A
T
T
A
A
(
(
S
S
e
e
r
r
i
i
a
a
l
l
A
A
T
T
A
A
)
)
The Serial ATA specification is designed to overcome speed limitations while enabling the storage interface to scale with the
growing media rate demands of PC platforms. Serial ATA is to replace parallel
ATA
with the compatibility with existing operating
systems and drivers, adding performance headroom for years to come. It is developed with data transfer rate of 150
Mbytes/second, and 300M/bs, 600M/bs to come. It reduces voltage and pins count requirements and can be implemented with
thin and easy to route cables.
S
S
M
M
B
B
u
u
s
s
(
(
S
S
y
y
s
s
t
t
e
e
m
m
M
M
a
a
n
n
a
a
g
g
e
e
m
m
e
e
n
n
t
t
B
B
u
u
s
s
)
)
SMBus is also called I
2
C bus. It is a two-wire bus developed for component communication (especially for semiconductor IC).
For example, set clock of clock generator for jumper-less motherboard. The data transfer rate of SMBus is only 100Kbit/s, it
allows one host to communicate with CPU and many masters and slaves to send/receive message.
S
S
P
P
D
D
(
(
S
S
e
e
r
r
i
i
a
a
l
l
P
P
r
r
e
e
s
s
e
e
n
n
c
c
e
e
D
D
e
e
t
t
e
e
c
c
t
t
)
)
SPD is a small ROM or
EEPROM
device resided on the DIMM or
RIMM
. SPD stores memory module information such as DRAM
timing and chip parameters. SPD can be used by
BIOS
to decide best timing for this DIMM or RIMM.
