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AWARD BIOS
3-13
Chipset Features
Æ
DRAM ECC Function
DRAM ECC
Function
Enabled
Disabled
This item lets you enable or disable DRAM ECC
function. The ECC algorithm has the ability to detect
double bit error and automatically correct single bit
error.
Chipset Features
Æ
CPU-to-PCI IDE Posting
CPU-to-PCI IDE
Posting
Enabled
Disabled
To enable or disable CPU to PCI IDE post write
cycle. The IDE write cycles will be queued in the
FIFO or buffer, and CPU can be released to do next
job. Disable it, if you find any IDE compatibility
problem.
Chipset Features
Æ
Video BIOS Cacheable
Video BIOS
Cacheable
Enabled
Disabled
Allows the video BIOS to be cached to allow faster
video performance.
Chipset Features
Æ
Video RAM Cacheable
Video RAM
Cacheable
Enabled
Disabled
This item lets you cache Video RAM A000 and B000.
Содержание MX3L
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