6
A
A
X
X
4
4
L
L
R
R
/
/
A
A
X
X
4
4
L
L
R
R
-
-
N
N
O
O
n
n
l
l
i
i
n
n
e
e
M
M
a
a
n
n
u
u
a
a
l
l
Bus Master IDE (DMA mode).........................................................................................................................................95
CNR (Communication and Networking Riser) ................................................................................................................96
CODEC (Coding and Decoding) ....................................................................................................................................96
DDR (Double Data Rated) SDRAM................................................................................................................................96
DIMM (Dual In Line Memory Module) ............................................................................................................................96
DMA (Direct Memory Access) ........................................................................................................................................96
ECC (Error Checking and Correction)............................................................................................................................97
EDO (Extended Data Output) Memory...........................................................................................................................97
EEPROM (Electronic Erasable Programmable ROM) ....................................................................................................97
EPROM (Erasable Programmable ROM) .......................................................................................................................97
EV6 Bus ........................................................................................................................................................................98
FCC DoC (Declaration of Conformity)............................................................................................................................98
FC-PGA (Flip Chip-Pin Grid Array) ................................................................................................................................98
Flash ROM ....................................................................................................................................................................98
FSB (Front Side Bus) Clock...........................................................................................................................................99
I
2
C Bus ..........................................................................................................................................................................99
IEEE 1394 .....................................................................................................................................................................99
Parity Bit ........................................................................................................................................................................99
PBSRAM (Pipelined Burst SRAM) ...............................................................................................................................100
PC-100 DIMM ..............................................................................................................................................................100
