LM721A
Service Manual Rev: A
Page
Page
Page
Page 21
21
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21 of
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of
of 59
59
59
59
C214
0.1uF/16V
C203
0.1uF/16V
GND
GND
SDA
C219
0.1uF/16V
R206
10K£[ 1/16W
R207
10K£[ 1/16W
RXC+
P.2
RMADDR14
DHS_LP
OR3
DEN
R246
NC
Hydis200
R231=10K
R231=10K
R238=NC
AU EN05
R231=10K
R232=10K
R238=10K
RMADDR12
R204
2.7K£[ 1/16W
FB210
60
C239
0.1uF/16V
OCM_START
x
ROM_ADDR13
+PV
EG0
RMADDR1
R221
10K£[ 1/16W
GND
ER2
OG1
/ROM_WE
C220
0.1uF/16V
C210
0.1uF/16V
C232
0.1uF/16V
ER0
ER6
+
C256
100uF/16V
gm5120
E
gm5120
MOZO
C
3
6
Friday, December 06, 2002
Title
Size
Document Number
Rev
Date:
Sheet
of
RMADDR4
DEN
C241
0.1uF/16V
R208
10K£[ 1/16W
OB6
C208
0.1uF/16V
GND
+A3.3V
OR4
RMADDR5
R232
10K
+A3.3V
+A3.3V
GPIO3
R205 1K£[ 1/16W
HOST_PORT_EN
SET
OB[0..7]
P.5
OG7
RMADDR15
DIGITAL PORT
EB4
RMADDR9
C205
0.1uF/16V
AGND
GND
GND
RMDATA0
EG6
ROM_ADDR(4:0)
RMDATA0
OG0
C233
0.1uF/16V
VS
P.2
RMADDR3
EG7
OB4
Determines polarity of HCLK signal
DVS
C207
0.1uF/16V
+PV
GND
PWM0
P.4
OB7
C236
0.1uF/16V
+
C224
22uF/16V
GPIO4/UART_DI
DDC_SCL
P.2
R214
10K£[ 1/16W
Reset
Circuit
RMADDR2
RMADDR10
EG3
DE/PD
P.5
GPIO2
P.4
EG[0..7]
P.5
X201
14.318MHz
1
2
+A3.3V
+3.3V
3.3V_DDDS
R230
NC
FB205
600OHM
If using 6-wire host protocol, program this bit to 0
Dual Input
R237=10K
Analog only
R237=NC
RXC-
P.2
/ROM_WE
GPIO7
P.4
BLUE-
P.2
OR1
R247
10K
HOST_PROTOCOL
GREEN-
P.2
DDC_SDA_A
P.2
EB5
RMDATA7
RP203
33£[ 1/16W
1
2
3
4
8
7
6
5
FB208
0
STDBY
GPIO7
FLASH/ Prom-Jet Socket
AGND
GND
GND
+A5V
BANK0
RMDATA5
CP202
2P
1
2
3
4
5
6
7
8
+
C222
22uF/16V
RX0+
P.2
EB[0..7]
P.5
VGA_PG
P.2
RMADDR1
DELETE 721
GPIO6
EB2
SCLPOL
K/E Select
OR[0..7]
P.5
GPIO3
P.4
RMADDR8
EB1
RMADDR7
+
C245
22uF/16V
EB6
RMDATA3
ROM_ADDR8
3.3V_DVI
RX2+
P.2
BLUE+
P.2
RMADDR5
R235
0£[ 1/16W
RMDATA3
RMADDR11
OG3
RMADDR2
GREEN+
P.2
OG[0..7]
P.5
HS
P.2
R226
NC
DVI_PLUG
P.2
RX0-
P.2
Reserved
ROM_ADDR(12:10)
OPTION FOR 5115
+A5V
+A3.3V
+A3.3V
GND
VOL
OB1
RMADDR15
EB0
DESCRIPTION
GPIO8
P.4
GPIO5/UART_DO
DDC_SCL_A
P.2
MUTE
OB3
U203.117
C231
0.1uF/16V
R237
10K
RMADDR6
+
C229
100uF/16V
C247
5pF
CN202
NC
1
2
3
4
+5V
TXD
RXD
GND
D201
LL4148
+A3.3V
RX2-
P.2
DDC_SDA
P.2
+
C230
22uF/16V
+2.5V
RMDATA1
R213
0£[ 1/16W
RX1-
P.2
OR0
RMADDR0
ROM_ADDR9
RS232
VGA_PLUG
U203.117
RX1+
P.2
DE/PD
P.5
GPIO5/UART_DO
RMADDR10
R236
NC
+
C259
100uF/16V
NAME
+PV
GPIO4/UART_DI
C254
NC
C217
0.1uF/16V
/ROM_WE
UART_DI
P.2
RMADDR8
/ROM_WE
TCLK
RMDATA6
FB207
600OHM
C253
22pF
C234
0.1uF/16V
+
C258
100uF/16V
RMADDR6
SCL
RED-
P.2
RMDATA4
ROM_OEn
DVI_PLUG
C201
0.1uF/16V
R239
NC (4.7K)
R220
NC
ROM_ADDR7
Available for reading from a status register
GND
+PV
ER3
RMDATA7
RMDATA6
RMADDR12
+A3.3V
UART_DO
P.2
32-Pin PLCC Socket
ADDRESS
ROM_ADDR6
RMADDR13
RMADDR11
FB206
600OHM
DHS
P.5
6/24
PPWR
P.5
RMADDR4
RMDATA2
RMADDR12
TCON_OSP
U204
M24C16-MN6T
1
2
3
4
5
6
7
8
A0
A1
A2
VSS
SI
SCK
WP
VCC
R201
10K£[ 1/16W
C248
0.1uF/16V
GND
AGND
GND
GND
GND
GPIO10
DISP_CLK P.5
C263
NC
C202
0.1uF/16V
1
GPIO(22:16) is on "Host Port" pins
RMADDR8
OB5
C225
0.1uF/16V
ER4
USER_BITS(4:0)
ROM_ADDR5
+A3.3V
RMADDR14
R227
NC
GND
+2.5V
SCL
4/29 ADD S/W TEST PBIAS CONTROLL
OB2
+PV
ER5
BANK0
C244
0.1uF/16V
x
1 = All 48K of ROM is in external ROM
GND
RMADDR3
OR2
RMADDR0
R212
NC
+A3.3V
GND
GND
RED+
P.2
C216
0.1uF/16V
BOOTSTRAP SIGNALS
Available for reading from a status register
LVDS_EN P.5
DEN
P.5
EG2
C246
5pF
C249
0.1uF/16V
C212
0.1uF/16V
ADD DEN SIGNAL PIN 4/28
ER[0..7]
P.5
RMADDR10
OB0
R215
10K£[ 1/16W
RMADDR7
C227
0.1uF/16V
AGND
GND
OG4
DVS
C240
0.1uF/16V
C213
0.1uF/16V
OSC_SEL
RMADDR4
3.3V_DVI
OR6
DEN
FB209
0
R223
10K£[ 1/16W
PBIAS
P.5
RMADDR13
R231
10K
GND
RMADDR9
TCON_OPOL
ER7
RMDATA5
3.3V_SDDS
/RESET
+
C221
22uF/16V
R241
NC
+PV
C228
0.1uF/16V
+
C237
100uF/16V
1 = OCM becomes active after OCM_CLK is stable
0
1
NC
GND
FB201
0
C226
0.1uF/16V
CP201
22P
1
2
3
4
5
6
7
8
+
C250
22uF/16V
C238
0.1uF/16V
FB204
600OHM
DVS
U202 W39F010P-70P
3
29
28
4
25
23
26
27
5
6
7
8
9
10
11
12
21
20
19
18
17
15
14
13
24
31
32
1
16
2
30
22
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE
WE
VCC
NC
GND
A16
NC/A17
CE
DVS
P.5
EG1
C250, C252 CHANGE EE, ADD R238---PWM 4/24
+5V
RMADDR3
OR7
GND
RMADDR2
R234
NC
FB202
0
EB7
U203.115
0 = XTAL and TCLK pins are connected
x
0
RMADDR0
R233
NC
R240
47£[ 1/16W
OG2
OR5
Int_Test
U203
PQFP208
GM2120
171
170
167
166
163
162
179
180
185
186
191
192
151
152
40
41
42
43
44
45
46
47
49
50
51
52
118
115
117
116
195
194
174
120
121
122
123
124
125
126
127
128
206
207
208
1
205
204
5
4
6
7
48
39
201
25
24
23
22
19
18
17
16
15
8
35
34
33
32
31
30
29
28
9
10
14
12
13
11
36
155
153
165
169
161
158
157
178
2
20
53
67
81
97
111
129
26
88
134
203
176
113
114
175
182
184
188
190
197
198
199
150
149
148
146
144
141
139
145
140
137
136
3
21
38
54
68
82
98
112
130
89
133
202
135
156
154
177
183
189
147
143
138
200
159
61
62
65
66
69
70
71
72
94
93
75
76
77
78
79
80
74
73
85
86
87
90
91
92
84
83
95
96
99
100
101
102
64
63
105
106
107
108
109
110
104
103
119
27
131
142
132
60
59
58
57
56
55
37
160
164
168
172
173
181
187
193
196
RED+
RED-
GREEN+
GREEN-
BLUE+
BLUE-
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
XTAL
TCLK
GPIO0/PWM0
GPIO1/PWM1
GPIO2/PWM2
GPIO3/TIMER1
GPIO4/UART_D1
GPIO5/UART_D0
GPIO6/EXTCLK
GPIO7
GPIO10/TCON_ROE3
GPIO11
GPIO12
GPIO13
DCLK/TCON_OCLK
DEN/TCON_ECLK
DVS/TCON_FSYNC
DHS/TCON_LP
RXC-
RXC+
REXT
TCON_OPOL
TCON_OINV
TCON_ESP
TCON_EPOL
TCON_EINV
TCON_RSP2
TCON_RSP3
TCON_RCLK
TCON_ROE
GPIO20/HDATA3
GPIO19/HDATA2
GPIO18/HDATA1
GPIO17/HDATA0
GPIO16/HFS
GPIO22/HCLK
RESETn
GPIO21/IRQn
DDC_SCL
DDC_SDA
GPIO9/TCON_ROE2
GPIO8/IRQINn
CLKOUT
ROM_ADDR0
ROM_ADDR1
ROM_ADDR2
ROM_ADDR3
ROM_ADDR4
ROM_ADDR5
ROM_ADDR6
ROM_ADDR7
ROM_ADDR8
ROM_ADDR15
ROM_DATA0
ROM_DATA1
ROM_DATA2
ROM_DATA3
ROM_DATA4
ROM_DATA5
ROM_DATA6
ROM_DATA7
ROM_ADDR14
ROM_ADDR13
ROM_ADDR9
ROM_ADDR11
ROM_ADDR10
ROM_ADDR12
ROM_OEn
VDD1_ADC_2.5
VDD2_ADC_2.5
AGND_GREEN
AGND_RED
AGND_BLUE
AGND_ADC
SGND_ADC
AGND_RX2
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
CVDD_2.5
CVDD_2.5
CVDD_2.5
CVDD_2.5
VDD_RX2_2.5
PPWR
PBIAS
AGND_IMB
VDD_RX1_2.5
AGND_RX1
VDD_RX0_2.5
AGND_RX0
AGND_RXC
AGND_RXPLL
VDD_RXPLL_2.5
AVDD_RPLL
AVSS_RPLL
VDD_DPLL_3.3
AVDD_SDDS
VDD_SDDS_3.3
AVDD_DDDS
VDD_DDDS_3.3
AVSS_SDDS
AVSS_DDDS
HSYNC
VSYNC
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
RVSS
CVSS
CVSS
CVSS
CVSS
GND1_ADC
GND2_ADC
GND_RX2
GND_RX1
GND_RX0
VSS_DPLL
VSS_SDDS
VSS_DDDS
N/C
ADC_TEST
PD6/ER6
PD7/ER7
PD10/EG2
PD11/EG3
PD12/EG4
PD13/EG5
PD14/EG6
PD15/EG7
PD33/OG1
PD32/OG0
PD18/EB2
PD19/EB3
PD20/EB4
PD21/EB5
PD22/EB6
PD23/EB7
PD17/EB1
PD16/EB0
PD26/OR2
PD27/OR3
PD28/OR4
PD29/OR5
PD30/OR6
PD31/OR7
PD25/OR1
PD24/OR0
PD34/OG2
PD35/OG3
PD36/OG4
PD37/OG5
PD38/OG6
PD39/OG7
PD9/EG1
PD8/EG0
PD42/OB2
PD43/OB3
PD44/OB4
PD45/OB5
PD46/OB6
PD47/OB7
PD41/OB1
PD40/OB0
TCON_OSP
CVSS
Reserved
N/C
Reserved
PD5/ER5
PD4/ER4
PD3/ER3
PD2/ER2
PD1/ER1
PD0/ER0
RVDD
AVDD_ADC
AVDD_BLUE
AVDD_GREEN
AVDD_RED
AVDD_IMB
AVDD_RX2
AVDD_RX1
AVDD_RX0
AVDD_RXC
+A3.3V
GND
RMADDR14
SDA
RP201
120
1
2
3
4
8
7
6
5
+
C211
22uF/16V
3.3V_RGB
XTAL
RP202
33£[ 1/16W
1
2
3
4
8
7
6
5
C209
0.1uF/16V
U201
3
2
1
VCC
RSTN
GND
LED_GRN
P.5
+
C257
100uF/16V
R222
10K£[ 1/16W
If using 6-wire host protocol, program this bit to 1
1
OCM_ROM_CFG(1)
GND
+A5V
GPIO6
P.4
OG5
RMDATA1
OG6
ER1
Close to respective power Pins
Note:
panel selected
LED_ORANGE
P.5
EB3
C242
0.1uF/16V
RMADDR1
C215
0.1uF/16V
C218
0.1uF/16V
RMADDR11
EG5
AGND
GND
GND
RMDATA2
C235
0.1uF/16V
C204
0.1uF/16V
C223
0.1uF/16V
EG4
GPIO0/PWM0
USER_BITS(7:5)
x
ROM_ADDR14
RMADDR9
C206
0.1uF/16V
+
C243
100uF/16V
+
C255
22u/16V
RMDATA4
U203.115
TCON_OCLK
R218
1K
R238
NC
FB203
600OHM
Close to respective power Pins
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