Evaluation Board User Guide
UG-016
Rev. 0 | Page 7 of 28
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Figure 6. VisualAnalog, Main Window Expanded Display
4.
Program the FPGA of the HSC-ADC-EVALCZ board to a
setting other than the default setting as described in Step 3.
Then expand the VisualAnalog display and click the
Settings
button in the
ADC Data Capture
block (see Figure 6). The
ADC Data Capture Settings
box opens (see Figure 7).
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Figure 7. ADC Data Capture Settings, Board Settings Tab
5.
Select the
Board Settings
tab and browse to the appropriate
programming file. If you are using an encode rate <28 MSPS,
select
Octal_Low_Speed.bin
. If you are using an encode
rate >28 MSPS, select
Octal_High_Speed.bin
. Next, click
Program
; the DONE LED in the HSC-ADC-EVALCZ board
should then turn on. If more than two channels are required
to be displayed, select
High_Speed_Octal_synchronous_
capture.bin
. This canvas allows the user to display all the
channels at once. The drawback is that each FFT display is
only 8k points.
Exit the
ADC Data Capture Settings
box by clicking
OK
.
Set Up the SPI Controller
After the ADC data capture board setup has been completed,
set up the SPI Controller:
1.
Open the SPI Controller software by going to the
Start
menu or double-clicking the SPI Controller software
desktop icon. If prompted for a configuration file, select
the appropriate one. If not, check the title bar at the top of
the SPI Controller window to determine which configuration
is loaded. If necessary, choose
Cfg Open
from the
File
menu and select the appropriate configuration Note that
the
CHIP ID(1)
field should be filled to indicate whether
the correct SPI Controller configuration file is loaded (see
Figure 8).
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Figure 8. SPI Controller, CHIP ID(1) Box
2.
Click the
New DUT
button in the SPI Controller (see
Figure 9).
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9
NEW DUT BUT TON
Figure 9. SPI Controller, New DUT Button
Содержание UG-016
Страница 12: ...UG 016 Evaluation Board User Guide Rev 0 Page 12 of 28 08282 021 Figure 22 DUT Analog Input Circuits Continued...
Страница 13: ...Evaluation Board User Guide UG 016 Rev 0 Page 13 of 28 08282 022 Figure 23 DUT VREF and Decoupling...
Страница 15: ...Evaluation Board User Guide UG 016 Rev 0 Page 15 of 28 08282 024 Figure 25 Clock Circuitry...
Страница 17: ...Evaluation Board User Guide UG 016 Rev 0 Page 17 of 28 08282 026 Figure 27 Top Side...
Страница 18: ...UG 016 Evaluation Board User Guide Rev 0 Page 18 of 28 08282 027 Figure 28 Ground Plane Layer 2...
Страница 19: ...Evaluation Board User Guide UG 016 Rev 0 Page 19 of 28 08282 028 Figure 29 Power Plane Layer 3...
Страница 20: ...UG 016 Evaluation Board User Guide Rev 0 Page 20 of 28 08282 029 Figure 30 Power Plane Layer 4...
Страница 21: ...Evaluation Board User Guide UG 016 Rev 0 Page 21 of 28 08282 030 Figure 31 Ground Plane Layer 5...
Страница 22: ...UG 016 Evaluation Board User Guide Rev 0 Page 22 of 28 08282 031 Figure 32 Bottom Side...
Страница 27: ...Evaluation Board User Guide UG 016 Rev 0 Page 27 of 28 NOTES...