Analog Devices UG-016, Руководство пользователя

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Evaluation Board User Guide UG-016
Rev. 0 | Page 5 of 28
DEFAULT OPERATION AND
JUMPER SELECTION SETTINGS
This section explains the default and optional settings or modes
allowed on the evaluation board for the
AD9276 and AD9277 .
Power Circuitry
Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P601.
Analog Input Front-End Circuit
The evaluation board is set up for single-ended Kelvin
connection analog input with an optimum 50 Ω impedance
match of 18 MHz of bandwidth. For a different bandwidth
response, use the manual tune feature and antialiasing filter
settings.
VREF
VREF is set to 1.0 V. This causes the ADC to operate with the
internal reference in the 2.0 V p-p full-scale range. A separate
external reference option using the
ADR130 is also included on
the evaluation board. Populate R320 with a 0 Ω resistor and remove
C301. Note that ADC full-scale ranges less than 2.0 V p-p are
not supported by the AD9276 and AD9277.
RBIAS
RBIAS has a default setting of 10 kΩ (R304) to ground and is used
to set the ADC core bias current. However, note that using other
than a 10 kΩ, 1% resistor for RBIAS may degrade the performance
of the device, depending on the resistor chosen.
Clock Circuitry
The default clock input circuitry is derived from a simple
transformer-coupled circuit using a high bandwidth 1:1
impedance ratio transformer (T501) that adds a very low amount
of jitter to the clock path. The clock input is 50 Ω terminated
and ac-coupled to handle single-ended sine wave types of inputs.
The transformer converts the single-ended input to a differential
signal that is clipped before entering the ADC clock inputs.
The evaluation board is already set up to be clocked from the
crystal oscillator, OSC501. This oscillator is a low phase noise
oscillator from Valpey Fisher (VFAC3HL-40MHz). If a different
clock source is desired, remove R503, set Jumper J501 to disable
the oscillator from running, and connect the external clock
source to the SMA connector, J503.
A differential LVPECL clock driver can also be used to clock the
ADC input using the
AD9516 (U501). Populate C528 and C529
with 0.1 μF capacitors and remove C506 and C507 to disconnect
the default clock path inputs. In addition, populate C511 and C512
with a 0.1 μF capacitor. The AD9516 has many SPI-selectable
options that are set to a default mode of operation. Consult the
AD9516 data sheet for more information about these and other
options.
PDWN
To enable the power-down feature, short P301 (Pin 3 to Pin 4)
to the on position (AVDD) on the PDWN pin.
STBY
To enable the standby feature, short P301 (Pin 1 to Pin 2) to the
on position (AVDD) on the STBY pin.
GAIN+, GAIN−
To change the VGA attenuation, drive the GAIN+ pin from 0 V
to 1.6 V on J401 using a linear supply. This uses the single-ended
method to change the VGA gain from 0 dB to 42 dB. U411 is
available for users who wish to drive the gain pins (GAIN±)
differentially. Install R426, R435, and R436 and remove C456,
C457, and R440 to connect the amplifier correctly. In differential
mode, a linear supply from −0.8 V to +0.8 V on J401 is required
to change the VGA gain from 0 dB to 42 dB.
If an external source is not available, remove R425, and install
R438 to use the on-board resistive divider (R439) for gain
adjustment in the single-ended case.
CWI/Q+, CWI/Q−
To view the CWI+/CWI− and/or CWQ+/CWQ− outputs,
configure the AD9276 and AD9277 to be in CW mode and
enable each channel via the SPI Controller program. Apply a
13 dBm, 20 MHz reference clock (4LO) on J303. Each enabled
channel is summed and is available through J402/J403.
DOUTx+, DOUTx−
If an alternative data capture method to the setup described in
Figure 2 is used, optional receiver terminations, R604 to R613, can
be installed next to the high-speed backplane connector, P604.