Analog Audio
1-10
ADSP-21375 EZ-KIT Lite Evaluation System Manual
Analog Audio
The AD1835A is a high-performance, single-chip codec featuring four ste-
reo digital-to-analog converters (DACs) for audio output and one stereo
analog-to-digital converters (ADCs) for audio input. The codec can input
and output data with a sample rate of up to 96 kHz on all channels. A
192 kHz sample rate can be used with one of the DAC channels.
The processor is interfaced with the AD1835A via the DAI port. The DAI
interface pins can be configured to transfer serial data from the AD1835A
codec in either time-division multiplexed (TDM) or two-wire interface
mode (TWI). For more information on the AD1835A connection to the
DAI, see
.
The master input clock (
MCLK
) for the AD1835A device can be generated
by the on-board 12.288 MHz oscillator or can be supplied by one of the
DAI pins of the processor. Using one of the pins to generate the
MCLK
, as
opposed to the on-board oscillator, allows synchronization of multiple
devices in the system. It is possible to disable the on-board audio oscillator
from driving the audio codec and the processor’s input pin. For instruc-
tions on how to configure the clock, refer to
The AD1835A codec can be configured as a master or as a slave, depend-
ing on the DIP switch settings. In master mode, the AD1835A drives the
serial port clock and frame sync signals to the processor. In slave mode,
the processor must generate and drive all of the serial port clock and frame
sync signals. For information on how to set up the mode, refer to
Setup Switch (SW3)” on page 2-11
.
The internal configuration registers of the AD1835A codec are configured
using the SPI port of the processor. The DPI pin 4 (
DPI4
register) is used
as the select for the device. For information on how to configure the mul-
tichannel codec, refer to the product datasheet at
http://www.analog.com/en/prod/0,2877,AD1835A,00.html
.
