Analog Devices SHARC ADSP-21375, Руководство пользователя

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External Memory
1-8 ADSP-21375 EZ-KIT Lite Evaluation System Manual
Table 1-1 provides start and end addresses of the board’s external
memories.
The parallel flash memory and SDRAM connect to the external memory
of the processor.
The SDRAM memory connects to the SDRAM controller of the proces-
sor. A set of programmable timing parameters is available to configure the
SDRAM banks to support slower memory accesses. Care must be taken
when configuring the SDRAM control registers. For more information
regarding the setup of the SDRAM controller, please refer to the
ADSP-21368 SHARC Processor Hardware Reference (includes
ADSP-21375). An example program is included in the EZ-KIT Lite
installation directory to demonstrate the SDRAM setup.
The SPI flash memory connects to the SPI port of the processor and
designates:
• DPI pin 5 (
DPI5
) as a chip select
• DPI pin 3 (
DPI3
) as the SPI clock
• DPI pin 1 (
DPI1
) as the
MOSI
• DPI pin 2 (
DPI2
) as the
MISO
Table 1-1. EZ-KIT Lite Evaluation Board External Memory
Start Address End Address Content
0x0020 0000 0x011F 0000
SDRAM memory (
~MS0
)
0x0400 0000 0x040F FFFF
Flash memory (
~MS1
)
0x0800 0000
0x0800 0000
0x08FF FFFF
0x0BFF FFFF
Unused chip select (
~MS2
) for non-SDRAM addresses
Unused chip select (
~MS2
) for SDRAM address
0x0C00 0000
0x0C00 0000
0x0CFF FFFF
0x0FFF FFFF
Unused chip select (
~MS3
) for non-SDRAM addresses
Unused chip select (
~MS3
) for SDRAM addresses