Analog Devices MAX77857, Руководство пользователя

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Evaluates: MAX77857 (WLP) MAX77857 Evaluation Kit
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•
Place the input capacitors (C
IN
) and output capacitors (C
OUT
) immediately next to the IN pin and OUT pin of the IC,
respectively. Since the IC operates at a high switching frequency, this placement is critical for minimizing parasitic
inductance within the input and output current loops, which can cause high voltage spikes and can damage the internal
switching MOSFETs.
•
Place the inductor next to the LX bumps (as close as possible) and make the traces between the LX bumps and the
inductor short and wide to minimize PCB trace impedance. Excessive PCB impedance reduces converter efficiency.
When routing LX traces on a separate layer (as in the examples), make sure to include enough vias to minimize trace
impedance. Routing LX traces on multiple layers is recommended to further reduce trace impedance. Furthermore,
do not let LX traces take up an excessive amount of area. The voltage on this node switches very quickly and an
additional area creates more radiated emissions.
•
Route LX nodes to their corresponding bootstrap capacitor (C
BST
) as short as possible. Prioritize C
BST
placement to
reduce trace length to the IC.
•
Connect the inner PGND bumps to the low-impedance ground plane on the PCB with vias placed next to the bumps.
Do not create PGND islands, as PGND islands risk interrupting the hot loops. Connect AGND and AGND island to the
low-impedance ground plane on the PCB (the same net as PGND).
•
Keep the power traces and load connections short and wide. This is essential for high converter efficiency.
•
Do not neglect ceramic capacitor DC voltage derating. Choose capacitor values and case sizes carefully. Refer to the
Output Capacitor Selection section in the MAX77857 IC data sheet and Tutorial 5527 for more information.
NON-HDI
VIA
8mil HOLE, 16mil PAD
6mil HOLE, 12mil PAD
LEGEND
COMPONE NT SIZES LISTED IN IMPE RIAL
UNLES S OTHERWISE SPE CIFIED
NOTE: PLACE C
IN
AND C
OUT
CLOSE TO THE IC TO MINIMIZE PA RASITIC INDUCTANCE WITHIN THE LOOP
+
C
IN
0805
IN
PGND
OUT
PGND
BST1
V
IO
V
L
FB
SCL
SDA
EN
SEL
*USING INTERNAL
FEEDB ACK RESISTORS
BST2
4.0mm x 4.0mm
LX1 LX2
**LAYOUT BASED
ON 7.0A I
LIM
CONFIGURATION
0603
0402
0805
AGND
C
IN
0805
C
OU
T
0805
C
O
U
T
0805
L
4.0mm x 4.0mm
C
BST1
0603
C
BST2
0603
C
V
IO
0
4
0
2
C
VL
0402
R
SEL
0402
Figure 15. Non-HDI PCB Layout Recommendation for 35 WLP Package with 4mm x 4mm Inductor