Evaluation Board
User Guide
UG-487
Rev. 0 | Page 3 of 10
PCB EVALUATION GOALS
This board is intended to achieve two goals.
1)
It will allow a user of the ADuM5010 or
ADuM6010 to exercise the functional capabilities
of the part. These include evaluation of bypass,
loading, power supply enable/disable control and
setting the adjustable output voltage level.
2)
This evaluation board demonstrates the EMI
mitigation techniques required to make a low
emissions design as set out in AN-0971.
The ADuM5010/ADuM6010 has a pin layout that is
compatible with the ADuM521x/ADuM621x families of
parts. These two additional device families include digital
isolation channels. One PCB design supports all four
families of parts. Many of the structures on the PCB that
support the digital channels are not populated for the
ADuM5010/ADuM6010 version of the PCB.
CONNECTORS
This evaluation system will be used to evaluate a variety of
different aspects of performance. Connections to power
and instrumentation are critical to performing accurate
measurements without creating artificial ringing,
reflections, ripple and EMI.
Two types of interconnect are provided, SMA edge
connectors and through hole signal ground pairs. Between
these two options, both temporary and permanent
connections to the board are easily be made. When coax
connections are desired, SMA connectors are available for
V
DDP
power input and V
ISO
output. These connectors were
chosen because they are low profile and provide excellent
mechanical connections to the PCB. Most lab equipment is
geared toward use of BNC connectors, so adaptors will be
required to use the on board connectors.
Power can be directly wired to the PCB via the through hole
connectors P6 and P7. These provide a power ground pair
with the power on the pin 1 hole. These through holes are
on 200mil centers which matches the pin spacing required
for Tektronix active probes. These positions can be used for
scope test points or direct wiring of power and ground.
PART CONFIGURATION STRUCTURES
The ADuM5010 and ADuM6010 have pins that must have
set inputs for the IC to operate properly. The evaluation
board allows all a full range of configuration options. On
the primary side, the PDIS pin must either be tied low to
enable the converter, or pulled high to disable the output
power and put the part in a standby state. Connector P3
allows a Jumper to be placed between pins 1-2 for to
disable the converter, or between pins 2-3 to enable the
converter. The header can be removed if an external logic
source will control the disable function and the signal can
be fed directly into position 2 of the header.
Control of the V
ISO
voltage is accomplished through a voltage
divider that’s center node is attached to the V
ADJ
pin as
shown in Figure 2. There are two options for setting the
output voltage supported on this evaluation board. A 20k
Ω
potentiometer is installed at R1A in series with a 16.5k
Ω
resistor at position R16A making a variable resistance to
V
ISO
of 16.5-36k
Ω
. A resistor to ground at position R14A
forms the lower leg of the voltage divider. This will give a
range of adjustment of V
ISO
from below 3.3V to above 5.0V.
Alternatively, if a fixed output voltage is desired, R16A can
be removed and a resistor can be installed in R13A that
combined with the existing resistance in R14A will form a
fixed voltage divider to set V
ISO
to a single voltage. Refer to
the data sheet for selection of resistor values.
BYPASS ON THE PCB
Several positions and structures are provided to allow
optimum bypass of the evaluation board. Provision has
been made for optional surface mount bulk capacitors to be
installed near the power connectors to compensate for long
cables to the power supply or external load. Parallel bypass
capacitors are installed near the ADuM5010 or ADuM6010
consisting of a 0.1uF and a 10uF capacitor for V
DDP
and V
ISO
.
The 0.1uF capacitors can be moved to positions on the back
side of the board if required.
The PCB also implements distributed capacitive bypass on
the primary side of the PCB. This consists of power and
ground fills on the top and bottom layers of the PCB on the
V
DDP
side of the board. This is one of the techniques
discussed in the EMI Mitigation section. It has the added
benefit of providing added bypass on the primary side of
the converter where the largest currents flow as well as RF
shielding.
PROVISION FOR LOADING
V
ISO
can be loaded three ways.
1)
An external load can be connected via the SMA
connector,
2)
A fixed resistor can be installed at R18A
3)
A surface mount resistor can be installed at R15A.
EMI MITIGATION
The PCB implements EMI mitigation techniques discussed
in
AN-0971
in order to demonstrate the recommended
board layout options for this device. These techniques
include;
Stitching capacitance
Capacitance between the primary and secondary power and
ground planes is the most effective way to reduce high
frequency emissions from an isoPower device. Figure 3
shows how the inner layers of a PCB can create this
stitching capacitance by overlapping inner layer metal to
create an extremely low inductance capacitance. The green
area shows the active coupling area.
Edge guarding
Providing guard rings laced together with vias on each layer
of the primary side reduces edge emissions from the PCB
stack-up. This addresses emissions due to large high
frequency vertical current flow through vias and traces near
