ADSP-BF707 EZ-KIT Lite Evaluation System Manual
1-9
Using ADSP-BF707 EZ-KIT Lite
With a CCES session running and connected to the EZ-KIT Lite via an
emulator, the DDR2 registers are configured automatically each time the
processor is reset through a soft reset using CCES. The values are used
whenever DDR2 is accessed through the debugger (for example, when
viewing memory or loading a program).
To disable the automatic setting of the DDR2 registers, select
Target
Options
from the
Session
menu in CCES and uncheck
Use XML reset
values
.
An example program is included in the EZ-KIT Lite installation directory
to demonstrate how to set up and access the DDR2 interface. For more
information on how to initialize the registers after a reset, refer to the
hardware reference manual.
SPI Flash
The ADSP-BF707 processor has three SPI interfaces: SPI0, SPI1, and
SPI2. SPI2 is connected to a Winbond W25Q32BC 32 Mb serial flash
memory with dual and quad SPI support. This flash is used for booting
and scratchpad space.
Quad mode is enabled by default. The processor flag signals,
PB_15
(SPI2_SEL1)
,
PB_13 (SPI2_D2)
, and
PB_14 (SPI2_D3)
are connected by
default and can be disconnected by using SoftConfig. Refer to
ware-Controlled Switches (SoftConfig)
for more information.
For more information, refer to the SPI flash example in the POST, which
is included in the ADSP-BF707 Board Support Package.
Содержание EZ-KIT Lite ADSP-BF707
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