Analog Devices EZ-KIT Lite ADSP-BF533, Руководство пользователя

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Using SDRAM Interface
2-4 ADSP-BF533 EZ-KIT Lite Evaluation System Manual
Using SDRAM Interface
The three SDRAM control registers must be initialized in order to use the
MT48LC4M16ATG-75 16M x 16 bits (32 MB) SDRAM memory. When
you are in a Vi+ EZ-KIT Lite session (that is, using the USB
debug interface and not using an emulator), the SDRAM registers are con-
figured automatically through the debugger. The values in
Table 2-2 are
used whenever Bank 0 is accessed through the debugger (for example,
when viewing memory windows or loading a program). The numbers were
derived for maximum flexibility and work for a system clock frequency
between 54 MHz and 133 MHz.
The
EBIU_SDGCTL
register can only be re-written within the user code by
first placing the chip in self refresh (see the ADSP-BF533 Blackfin Proces-
sor Hardware Reference ). Clearing the appropriate checkbox on the Target
Table 2-2. EZ-KIT Lite Session SDRAM Default Settings
1
1 54 MHz <= SCLK <= 133 MHz.
Register Value Function
EBIU_SDGCTL 0x0091998D
Calculated with SCLK = 133 MHz
16-bit data path
External buffering timing disabled
t
WR
= 2 SCLK cycles
t
RCD
= 3 SCLK cycles
t
RP
= 3 SCLK cycles
t
RAS
= 6 SCLK cycles
pre-fetch disabled
CAS latency = 3 SCLK cycles
SCLK1 disabled
EBIU_SDBCTL 0x00000013
Bank 0 enabled
Bank 0 size = 32 MB
Bank 0 column address width = 9 bits
EBIU_SDRRC 0x000001A0
Calculated with SCLK = 54 MHz
RDIV = 416 clock cycles