EVAL-ADuM5028EBZ
User Guide
UG-1263
Rev. A | Page 3 of 8
EVALUATION BOARD HARDWARE
USING THE EVALUATION BOARD
Figure 1 shows the EVAL-ADuM5028EBZ evaluation board.
The
ADuM5028
sample device can be powered directly or
through the on-board low dropout regulator (LDO). Either
power scheme can be used without modification to the EVAL-
ADuM5028EBZ evaluation board. The LDO input supply, Pin 1
of Screw Terminal P1 (marked VREG on the silkscreen), requires a
power supply voltage of 6 V to 9 V. The LDO generates the
required 5 V to the
ADuM5028
V
DDP
pin. The complete board
can be powered by a 9 V battery (when testing for electromagnetic
compatibility (EMC), for example). Alternatively, the
ADuM5028
device can be powered directly with a 5 V supply through Pin 2
of Screw Terminal P1 (marked VDDP on the silkscreen). In
both schemes, the power supply return connects to Pin 3 of
Screw Terminal P1 (marked GND1 on the silkscreen). The
jumper on JP1 must be installed to short JP1 Pin 3 and JP1 Pin4
to pull the PDIS pin low and enable the
ADuM5028
when no
external control signal is used. Installing the jumper on JP1 to
short JP1 Pin1 and JP1 Pin 2 pulls the PDIS input pin high,
which disables the
ADuM5028
device. The V
ISO
output voltage
is set to 5.0 V by installing a 0 Ω resistor in the R2 pull-up
position, or the V
ISO
output voltage is set to 3.3 V by installing a
0 Ω resistor in the R3 pull-down position.
PCB LAYOUT RECOMENDATIONS
The
ADuM5028
uses a 180 MHz oscillator frequency to pass
power through its chip scale transformers. Bypass capacitors are
required for several operating frequencies. Noise suppression
requires low inductance and a high frequency capacitor. Ripple
suppression and proper regulation require a large value capacitor.
These capacitors are most effective when connected directly
adjacent to the V
DDP
pin and the GND
1
pin, and directly adjacent to
the V
ISO
pin and the GND
ISO
pin. To suppress noise and reduce
ripple, a parallel combination of at least two capacitors is required.
The recommended capacitor values for V
DDP
are 0.1 µF and 10 µF.
The smaller capacitor must have a low equivalent series resistance
(ESR). Use of a ceramic capacitor is advised. The total lead length
between the ends of the low ESR capacitor and the input power
supply pin must not exceed 2 mm.
To reduce the level of electromagnetic radiation, increase the
impedance to high frequency currents between the V
ISO
pin and
the GND
ISO
pin and the PCB trace connections. Using this method
of emissions suppression controls the radiating signal at its
source by placing surface-mount ferrite beads in series with the
V
ISO
pin and GND
ISO
pin (see Figure 5). The impedance of the
ferrite bead is approximately 1.8 kΩ between the 100 MHz and
1 GHz frequency range. This impedance value reduces the
emissions at the 180 MHz primary switching frequency and the
360 MHz secondary side rectifying frequency and harmonics.
See Table 2 for examples of appropriate surface-mount ferrite
beads.
Table 2. Surface-Mount Ferrite Beads
Manufacturer
Part No.
Taiyo Yuden
BKH1005LM182-T
Murata Electronics
BLM15HD182SN1
To pass EN55022 Class B on a 2-layer PCB, the following layout
guidelines for
ADuM5028
are recommended (see Figure 2 and
Figure 5):
•
Place ferrite beads between the PCB trace or plane
connections and V
ISO
(Pin 6) and GND
ISO
(Pin 5).
•
Do not connect the V
ISO
load to a PCB power plane (see
Figure 5). Connect the V
ISO
load using a PCB trace.
•
Ensure V
ISO
(Pin 6) is connected first through the E2 ferrite
before connecting it to the V
ISO
load (see Figure 2).
•
Ensure GND
ISO
(Pin 5) is connected by a trace to the
GND
ISO
pins (Pin 7) on the inside (device side) of the C4
100 nF capacitor.
•
Ensure the C4 capacitor is connected between V
ISO
(Pin 6)
and GND
ISO
(Pin 5) on the device side of the E3 and E2
ferrite beads.
•
Ensure there is a keep out area in the PCB layout around
the E2 and E3 ferrites, as shown in Figure 2 (no PCB planes
under or alongside E2 and E3).
16695-
002
Figure 2. Layout Guidelines for EVAL-ADuM5028EBZ
•
Locate the power delivery circuit in close proximity to the
ADuM5028
device to ensure the V
DDP
trace is as short as
possible. The EVAL-ADuM5028EBZ PCB has a power
delivery circuit located on the PCB with a short trace from
the
ADP7104ACPZ
regulator output (U1) to V
DDP
(Pin 3).
This layout example minimizes the loop area in which high
frequency current can flow. An increase in the loop area
results in an increase in the emissions levels.
•
To improve emissions, use Murata BLM18HE152SN1D
ferrites (0603 size, SMD) for E1, E4, and E5, which are
1500 Ω at 100 MHz to 1 GHz. Other ferrites can be used
for E1, E4, and E5; however, because of the input power
requirements, they must be 0603 size ferrites.
