EVAL-ADN4651EB1Z/EVAL-ADN4652EB1Z
User Guide
One
Technology Way
•
P.O.
Box 9106
•
Norwood, MA 02062-9106, U.S.A.
•
Tel: 781.329.4700
•
Fax: 781.461.3113
•
www.analog.com
5 kV RMS, 600 Mbps LVDS Isolator (SOIC_W)
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. A | Page 1 of 13
FEATURES
Isolated ground planes (logic side and bus side)
Convenient connections through SMA terminals
3.3 V or 2.5 V power on Side 1 (V
IN1
/V
DD1
) and Side 2
(V
IN2
/V
DD2
)
Ground on Side 1 (GND
1
) and Side 2 (GND
2
)
LVDS input signals: D
IN1+
, D
IN1−
, D
IN2+
, D
IN2−
LVDS output signals: D
OUT1+
, D
OUT1−
, D
OUT2+
, D
OUT2−
Jumper-selectable supply power of 3.3 V or 2.5 V
Termination resistors on all LVDS drivers/receivers
EVALUATION KIT CONTENTS
evaluation board
DOCUMENTS NEEDED
data sheet
EQUIPMENT NEEDED
Signal generator
Oscilloscope
GENERAL DESCRIPTION
and
allow
quick and easy evaluation of the
low-voltage
differential signalling (LVDS) isolator without the need for external
components. The
Inc.,
i
Coupler® technology to combine a 2-channel isolator with an
LVDS receiver and driver into a single, 20-lead wide body SOIC
package. They are capable of running at data rates of up to 600
Mbps with very low jitter.
The evaluation board has separate ground and power planes for
each side of the isolator. This separation enables the evaluation
of the
with galvanic isolation between both
sides of the device. Jumper-selectable power supplies at 3.3 V or
2.5 V are required on each side of the
. Using
an on-chip LDO, 2.5 V can be provided from an external 3.3 V
power supply.
Complete information about the
which should be consulted in conjunction with this user guide
when using the evaluation boards.
