Analog Devices EVAL-ADAU1772Z, Руководство пользователя

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Evaluation Board User Guide UG-477
Rev. A | Page 13 of 28
SERIAL AUDIO INTERFACE
Serial audio signals in I
2
S, left justified, right justified, or TDM
format are available via the Serial Audio Interface Header J4. This
header also includes master clock input and output connection
pins. To use MCLK on the J4 header, first install a resistor across
the R2 pads. The R2 resistor is not populated from the factory.
To use an external MCLK, remove the R3 resistor from the board
to eliminate contention from the XTAL oscillator on the MCLK
line (see Figure 41).
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040
Figure 41. R2 and R3
TDM/I 2 S Stream
To use the serial audio outputs, connect the LRCLK, BCLK, and
SDATA lines to the appropriate MP pins on the evaluation board.
The connections can be located on the J4 header. The silk screen
above the header helps identify where to connect the clocks and
data (see Figure 42).
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041
Figure 42. Serial Audio Port
Once connected, use SigmaStudio to set the registers for the
desired operation. In the
Output/Serial Port tab, under the
Serial Port Control section, the settings can be manipulated to
create the specific data stream desired. These settings include
Serial Port FS (sample rate), Serial Port Mode , Serial Port
Format , LRCLK/BCLK Mode (slave or master), BCLK Data-
Change Edge , Bit Width in TDM mode BCLK Cycles per
Channel , Data IO on LSB/MSB , Unused TDM Outputs ,
LRCLK Mode (as pulse or 50% duty cycle), and LRCLK
Polarity (see Figure 43).
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042
Figure 43. Serial Port Control
If using TDM mode, ensure that the appropriate TDM output
channels have been enabled in the
TDM Output Channel
section (see Figure 44).
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043
Figure 44. TDM Output Channel