Analog Devices EVAL-ADAU1466Z, Руководство пользователя

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EVAL-ADAU1466Z User Guide UG-1135
Rev. 0 | Page 17 of 45
The schematic (see Figure 58) shows audio from input Channel 0
and Channel 1 connected to the input of a volume control block.
The volume is controlled by the value of the AUXADC1 channel,
which is controlled by the left potentiometer, R1.
The output of the auxiliary ADC on the ADAU1466 is a 10-bit
integer value in a 32-bit register. The first DSP Readback block,
before the left shift, displays the output of the ADC in 32.0 format,
which can be interpreted as 32 integer bits and 0 fractional bits.
When the potentiometer is turned fully counter clockwise, this
block reads back the minimum ADC output value of 0. When
the potentiometer is turned fully clockwise, this block reads back
the maximum ADC output value of 1023 (within the range of
the component tolerance).
The native audio format of the ADAU1466 is 8.24. In this example,
the volume control multiplies the input signal by a fractional
value ranging from 0 (silence) to 1 (unity gain). Therefore, the
control signal from the ADC must be left shifted 14 bits to scale
the maximum value appropriately.
The second DSP Readback block, after the left shift, displays the
output of the ADC in 8.24 format, which may be interpreted as
8 integer bits and 24 fractional bits. When the potentiometer is
turned fully counter clockwise, this block reads back the minimum
ADC output value of 0. When the potentiometer is turned fully
clockwise, this block reads back the maximum ADC output value
of 1 (within the range of the component tolerance).
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Figure 58. Completed Signal Flow with DSP Read Back