EVAL-ADAQ23875FMCZ
User Guide
UG-1896
Rev. 0 | Page 5 of 26
EVALUATION BOARD CONNECTORS
The functional descriptions for all the connectors (including a
160-pin FMC connector used to interface with the
SDP-H1
) used
on the EVAL-ADAQ23875FMCZ are listed in Table 2 and
Table 3, respectively.
There are several test points and single in line (SIL) headers on
the EVAL-ADAQ23875FMCZ. These test points provide easy
access to on-board signals for troubleshooting and evaluation
purposes.
Table 3. On-Board Connectors
Connector
Function
J1
CLKIN input
J2
EXT_CNV-
J3
External CLK input
J4
VIN+
Analog input V+
VIN−
Analog input V−
+3P3V
External power supply
P5
SDP-H1
FMC connector
Table 4. 160-Pin FMC Connector (P5) Details
Signals
Function
100 MHz low jitter positive line of differential pair for carrying clock signals from the daughter board.
OSC_CLK−
100 MHz low jitter negative line of differential pair for carrying clock signals from the daughter board.
CLK±
µModule CLK input signals connected to FPGA Bank 2.
1, 2
CLK−
µModule CLK input signals connected to FPGA Bank 2.
1, 2
DCO+
Positive line of differential pair for carrying clock signals from the daughter board.
DCO−
Negative line of differential pair for carrying clock signals from the daughter board.
F
User defined signals connected to FPGA Bank 2.
1, 2
FPGA_CNV−
User defined signals connected to FPGA Bank 2.
1, 2
DA±
User defined signals connected to FPGA Bank 2.
1
DB±
User defined signals connected to FPGA Bank 2.
1
+3P3V_FMC
3.3 V (3 A) power supply to daughter board.
SCL
I
2
C clock line for reading FMC EEPROM.
SDA
I
2
C data line for reading FMC EEPROM.
GA0
I
2
C geographical Address 0. Must be connected to Address Pin A1 of the FMC EEPROM.
GA1
I
2
C geographical Address 1. Must be connected to Address Pin A0 of the FMC EEPROM.
3P3VAUX
3.3 V (20 mA) power supply for powering only the FMC EEPROM.
PG_C2M
Active high signal indicating that the 12P0V, 3P3V, and VADJ power supplies are turned on.
CNV_EN
User defined signals connected to FPGA Bank 2.
1
1
User defined signals with a P suffix can be used as the positive pin of the differential pair. User defined signals with an N suffix can be used as the negative pin of the
differential pair. For further information, see the VITA 57 specification.
2
User defined signals with a CC suffix are the preferred signal lines on which to transmit clock signals from the controller board to the daughter board. These signal lines are
connected to global clock lines on the FPGA, but they can also be used to carry any other user defined signal. For further information, see the VITA 57 specification.
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