ADT7476
Rev. B | Page 52 of 72
How Fan Presence Detect Works
Typically, 4-wire fans have an internal pull-up to 4.75 V ± 10%,
which typically sources 5 mA. While the detection cycle is on,
an internal current sink is turned on, sinking current from the
fan’s internal pull-up. By driving some of the current from the
fan’s internal pull-up (~100 μA), the logic buffer switches to a
defined logic state. If this state is high, a fan is present; if the
state is low, no fan is present.
Note that the PWM input voltage should be clamped to 3.3 V.
This ensures that the PWM output is not pulled to a voltage
higher than the maximum allowable voltage on that pin (3.6 V).
FAN SYNC
When two ADT7476s are used in a system, it is possible to
synchronize them so that one PWM channel from each device
can be effectively OR’ed together to create a PWM output that
reflects the maximum speed of the two OR’ed PWMs. This
OR’ed PWM can in turn be used to drive a chassis fan. See the
Analog Devices website, located at
www.analog.com, for
information about the Fan sync function.
STANDBY MODE
The ADT7476 is specifically designed to respond to the STBY
supply. In computers that support S3 and S5 states, the core
voltage of the processor is lowered in these states. When
monitoring THERM, the THERM timer should be disabled
during these states.
When the V
CCP
voltage drops below the V
CCP
low limit, the
following occurs:
1.
Status Bit 1 (V
CCP
) in Status Register 1 is set.
2.
SMBALERT is generated, if enabled.
3.
THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
Once the core voltage, V
CCP
, goes above the V
CCP
low limit,
everything is re-enabled and the system resumes normal
operation.
XNOR TREE TEST MODE
The ADT7476 includes an XNOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XNOR tree, it is
possible to detect opens, or shorts, on the system board.
The XNOR tree test is invoked by setting Bit 0 (XEN) of the
XNOR tree test enable register (0x6F).
Figure 66 shows the signals that are exercised in the XNOR tree
test mode.
PWM1/XTO
PWM3
PWM2
TACH4
TACH3
TACH2
TACH1
VID4
VID3
VID2
VID1
VID0
05382-067
Figure 66. XNOR Tree Test
POWER-ON DEFAULT
When the ADT7476 is powered up, monitoring is off by default
and the PWM outputs go to 100%. All necessary registers then
need to be configured via the SMBus for the appropriate
functions to operate.
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