Circuit Note
Rev. A | 3 of 6
PHYSICAL LAYER—MAC INTERFACE
The MAC interface is the wired medium on the CN0506 and there
are three MAC interface options, RGMII, RMII, or MII. RGMII
supports all speeds up to 1000 Mbps, while MII and RMII support
10 Mbps and 100 Mbps, respectively. RGMII is the default interface
on the CN0506.
The two ways to choose which MAC interface to use is either
by hardware strapping external resistors or by using a software
register configuration. MACIF_SEL0 and MACIF_SEL1 are multi-
functional pins within the ADIN1300 (see the ADIN1300 data sheet
for additional information). For the CN0506, the MACIF_SEL0 and
MACIF_SEL1 pins can be configured to select the MAC interface
according to
. Note that the MACIF_SEL0 and MACIF_SEL1
pins have weak internal pull-down resistors. Therefore, if there are
no external strapping resistors, the default MAC interface is RGMII
with a 2 ns delay.
Table 1. MAC Interface Selection
MAC Interface Selection
MACIF_SEL1
MACIF_SEL0
RGMII RXC/TXC, 2 ns Delay
Low
Low
RGMII RXC only, 2 ns Delay
High
Low
MII
Low
High
RMII
High
High
In CN0506, the MAC interface selection is done via software config-
uration by using the GE_RGMII_CFG and GE_RMII_CFG registers
within the ADIN1300. There are also footprints for external pull-up
and pull-down resistors if users rather configure the MAC interface
within the hardware. However, the resistors are not installed; there-
fore, the PHY powers up on the EVAL-CN0506-FMCZ with the
default RGMII interface.
PHY ADDRESS
There are four PHY address pins (PHYAD_x) that allow users to
configure the PHY to any of the 16 PHY addresses. The PHY ad-
dressing enables a system to have up to 16 individually controllable
channels from a single controller.
The EVAL-CN0506-FMCZ is currently hardwired to specific ad-
dresses, but it can be changed by altering the configuration resis-
tors for each of the channels. Based on the current settings, Chan-
nel 1 is assigned with Address 0001 and Channel 2 is assigned
with Address 0010.
PROGRAMMABLE MAC INTERFACE CLOCK
The ADIN1300 has three MAC interface options namely, MII, RMII
or RGMII. For RGMII and MII interfaces, a 25 MHz clock is required
for the ADIN1300, while the RMII requires an external 50 MHz
clock. In a user application, the user can choose to place a 25 MHz
crystal close to the XTAL_I and XTAL_O pins; or for the RMII use
case, the host controller, MAC interface, or switch can provide the
required 50 MHz clock directly to the PHY.
The EVAL-CN0506-FMCZ includes two programmable I
2
C clocks
(Y1 and Y2) from 100 kHz to 125 MHz to support each of the
ADIN1300 clock needs for the different MAC interfaces.
By default, the clock for each channel is set to 25 MHz on power
up. When using the RMII MAC interface, the clock can be program-
med to 50 MHz.
Both clocks have the same I
2
C address, but by using an I
2
C
address translator,
, these clocks can be programmed
individually to be different from each other. The LTC4316 translates
each incoming bit by XORing the incoming address to a user
configurable translation byte set by a resistive divider network of the
chip.
MDI INTERFACE—INTEGRATED MAGNETICS
The MDI interface connects the ADIN1300 to the Ethernet network,
typically through a transformer and RJ45 connector. The CN0506
uses RJ45 connectors with integrated magnetics. Integrated mag-
netics in the RJ45 connectors typically improve electromagnetic
interference (EMI) shielding and have a smaller footprint, requiring
shorter trace routing when compared to using discrete magnetics.
Integrated magnetics consist of the RJ45 connector, common-mode
chokes, isolation transformers, LEDs, decoupling capacitors, and
termination resistors. Designs may opt to use discrete magnetics
due to different overvoltage requirements in designs, or if a need for
a different layout for a specific EMI is required.
POWER SUPPLIES
To reduce the number of power supplies, the power requirement for
the analog circuitry of ADIN1300, MDIO, and MAC interfaces are
taken from the 3.3 V rails of the FPGA through a ferrite bead to
reduce noise into the system.
The digital core of the ADIN1300 requires a 0.9 V supply. This sup-
ply is derived on board from the 3.3 V rail using the
width modulation (PWM), step-down, dc-to-dc converter, which
converts the 3.3 V supply from the FPGA into 0.9 V, consuming a
maximum of 0.45 W from the carrier.
