Analog Devices Blackfin A-V EZ-Extender, Руководство пользователя

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Blackfin A-V EZ-Extender Manual 2-11
A-V EZ-Extender Hardware Reference
PPI Clock Setup Jumpers (JP4.1/2, JP4.3/4, JP4.5/6,
JP4.7/8)
The
PPI_CLK
signals of
PPI0
and
PPI1
are configured by the clock setup
jumpers (see Table 2-5 ). For more information, refer to Figure 2-1 on
page 2-4 .
PPI0 D8–15 Enable Jumper (JP5.1/2)
The
JP5.1/2
jumper, when is not installed, disables the upper eight bits of
the
PPI0
data bus. This allows the signals connected to the upper eight bits
of the PPI data bus of the EZ-KIT Lite to be used elsewhere on the board.
To disable and re-use the upper eight bits of the
VID_IN
and
PPI0
data
busses, install
JP5.1/2
.
Table 2-5. PPI Clock Setup Jumper Results
Jumper Location Result
JP4.1/2
Connects
EXT_VID_CLK
to the on-board 27 MHz oscillator. For more infor-
mation about the
EXT_VID_CLK
signal, see the
JP4.3/4
description.
JP4.3/4
Connects
PPI0_CLK
to the
EXT_VID_CLK
net. The
EXT_VID_CLK
net is the
external clock, which drives the input clock of all three camera module con-
nectors, plus the flat panel display connector. Depending on the
JP4
jumper
installation,
EXT_VID_CLK
can be generated by the
PIXEL_CLK
net, the
VDEC_CLKOUT
net, a socket (
U8
), or the on-board 27 MHz oscillator.
JP4.5/6
Connects
VDEC_CLKOUT
to
PPI0_CLK
;
VDEC_CLKOUT
drives the
PPI0
clock
when the video decoder is used.
JP4.7/8
Connects the
PIXEL_CLK
net, which is an output from the three camera inter-
faces, to
PPI0_CLK
.