Analog Devices ADV8003, Руководство по оборудованию

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ADV8003 Hardware Manual
Rev. B, August 2013 110
Primary
VSP
Secondary
VSP
Primary VSP
dpll clock
Secondary VSP
dpll clock
Primary
VSP
Secondary
VSP
Primary VSP
dpll clock
Secondary VSP
dpll clock
Figure 41: PVSP/SVSP Output Clock Configure
For the PVSP and SVSP, the correct clocks must be configured manually. This can be done using the DPLL period registers, which allows
the user to program the sampling rate for the appropriate output format by I
2 C. The equation for calculating this I 2 C value is provided in
Equation 1 .
MHz
period phase dpll
27 12 64
1
_ _
× ×
≡
Equation 1: Calculating DPLL Phase Period
Once the dpll_phase_period is calculated,
Equation 2 is used to calculate the dpll_clock_period.
period phase dpll
period clock output
period clock dpll
_ _
2 _ _
_ _
22
×
≡
Equation 2: Calculating DPLL Clock Period
where output_clock_period is the period of the desired output sampling frequency.
For example, for HD video, the output clock sampling frequency would be 148.5 MHz. This equation returns a decimal value. Once
calculated, this should be converted to hex and written to
pvsp_vid_clk_period[33:0] and svsp_vid_clk_period[33:0] . Table 8 outlines
some common resolutions and their associated dpll_clock_period values.
Table 8: Example Values for dpll_clock_period
Active Resolution Frame Rate (Hz) Sampling
Frequency (MHz) dpll_clock_period
(Hex)
720 x 480i 29.97 13.5 0x180000000
720 x 480p 59.94 27 0x0C0000000
720 x 576i 25 13.5 0x180000000
720 x 576p 50 27 0x0C0000000
960 x 480i 29.97 18 0x120000000
960 x 576i 25 18 0x120000000
1280 x 720p 59.94 74.175 0x045E386DC
1280 x 720p 60 74.25 0x045D1745D
1920 x 1080i 29.97 74.175 0x045E386DC
1920 x 1080i 30 74.25 0x045D1745D
1920 x 1080p 59.94 148.35 0x022F1C36E
1920 x 1080p 60 148.5 0x022E8BA2F
1920 x 1080i 25 74.25 0x045D1745D