background image

ADV7619 Required Settings Manual

 

ADV7619 Reference Manual

 

 

Rev. 1.8 | Page 5 of 14 

2

 

HDMI RECEIVER REGISTER SETTINGS 

Different register settings are required to configure the HDMI Receiver depending on the resolution it receives. These required settings are 

listed below for the respective resolutions. Note that these settings do not include the TMDS Equalizer settings, which are described in Section 
3. Also note that these required settings are not the only settings needed to configure the ADV7619.  
Please refer to the latest ADV7619 scripts file revision for all the settings required to configure the ADV7619 for a specific mode, and for the 
sequence in which these writes must be done.  
 
 

2.1

 

INPUT VIDEO PIXEL CLOCK FREQUENCY ≤ 170MHZ 

The following two categories of settings are required for input video resolutions with a pixel clock of less than or equal to 170 MHz. 
 

2.1.1

 

480i, 576i, 480p and 576p Resolutions up to a 36-bit color depth 

The following settings are required for the 480i, 576i, 480p and 576p resolutions with color depths between 24-bit and 36-bit. For these 
resolutions, the data is processed through the CP core. 
 

CP Map and HDMI Map 

 

44 6C 00 

ADI Required Write 

68 C0 03 

ADI Required Write 

68 03 98 

ADI Required Write 

68 10 A5 

ADI Required Write 

68 1B 08 

ADI Required Write 

68 45 04 

ADI Required Write 

68 97 C0 

ADI Required Write 

68 3D 10 

ADI Required Write 

68 3E 69 

ADI Required Write 

68 3F 46 

ADI Required Write 

68 4E FE 

ADI Required Write 

68 4F 08 

ADI Required Write 

68 50 00 

ADI Required Write 

68 57 A3 

ADI Required Write 

68 58 07 

ADI Required Write 

68 6F 08 

ADI Required Write 

68 84 03 

ADI Required Write 

 
 
 
 
 
 
 
 

 

 

Содержание ADV7619

Страница 1: ...is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Information contained within...

Страница 2: ...gs 5 2 1 Input Video Pixel Clock Frequency 170MHz 5 2 2 Input Video Pixel Clock Frequency 170MHz 6 3 TMDS Equalizer Settings 7 3 1 Input Video Pixel Clock Frequency 170MHz 7 3 2 Input Video Pixel Cloc...

Страница 3: ...ed to TOTAL_LINE_LENGTH 2 12 14 Revision 1 5 to 1 6 Updated overall format of the document Section 1 1 Recommended I2C Addresses renamed Section 1 ADV7619 I2C addresses and content updated Section 1 2...

Страница 4: ...A 6C EDID Map Address set to 0x6C 98 FB 68 HDMI Map Address set to 0x68 98 FD 44 CP Map Address set to 0x44 The I2 C addresses are programmed in the IO Map at the registers shown above The ADV7619 IO...

Страница 5: ...OCK FREQUENCY 170MHZ The following two categories of settings are required for input video resolutions with a pixel clock of less than or equal to 170 MHz 2 1 1 480i 576i 480p and 576p Resolutions up...

Страница 6: ...red Write 68 84 03 ADI Required Write 2 2 INPUT VIDEO PIXEL CLOCK FREQUENCY 170MHZ The following settings are required for input video resolutions with a pixel clock of greater than170 MHz For these r...

Страница 7: ...i 576i 480p and 576p resolutions with color depths between 24 bit and 36 bit HDMI Map 68 85 11 ADI Required Write 68 86 9B ADI Required Write 68 89 03 ADI Required Write 68 9B 03 ADI Required Write 68...

Страница 8: ...ADI Required Write 4 LOW VERTICAL FREQUENCY FORMATS To process low frame rate video formats such as 720p24 720p25 and 720p30 the NEW_VS_PARAM bit should be set Figure 2 illustrates how to proceed to d...

Страница 9: ...TING TMDSPLL_LCK_X_MB1 or TMDSPLL_LCK_X_MB2 1 ENABLE NEW_TMDS_FRQ_ST INTERRUPT BY SETTING NEW_TMDS_FRQ_MB1 or NEW_TMDS_FRQ_MB2 TMDS FREQUENCY READ BACK NOT VALID OR STABLE READ THE TMDS FREQUENCY TMDS...

Страница 10: ...68 83 FC Enable clock termination manually on both part A and port B The clock termination can also be enabled automatically This can be done by setting TERM_AUTO HDMI Map Register 0x01 0 to 1 8 FREE...

Страница 11: ...ditional power savings can be achieved by using the following writes Disable ring oscillator 68 48 01 Power down DDC pads 68 73 03 10 PACKET DETECTION The ADV7619 does not generate an interrupt when a...

Страница 12: ...END VS_INFO_ST has been set indicating that VS_INFO_RAW has changed Is VS_INFO_RAW high IO Map 0x60 4 YES NO Clear status bit IO Map 0x62 4 Enable Software timer for max allowed packet repeat time tim...

Страница 13: ...O NO Is Timer Enabled Is Timer Enabled Is time max allowed packet repeate time YES YES YES Is VS_INFO_RAW bit high IO Map 0x60 4 Clear VS_INFO_RAW Infoframe Map 0xEC 0x81 Enable Interrupt Mask IO Map...

Страница 14: ...loped by Philips Semiconductors now NXP Semiconductors HDMI the HDMI Logo and High Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States an...

Отзывы: