Analog Devices ADSP-BF526 EZ-Board, Руководство пользователя

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ADSP-BF526 EZ-Board Evaluation System Manual 2-3
ADSP-BF526 EZ-Board Hardware Reference
digipot, which is configurable over the 2-wire interface (TWI) signals.
Refer to the power-on-self test (POST) example in the ADSP-BF526
installation directory for information on how to set up the TWI interface.
The core voltage and clock rate can be set on the fly by the processor. The
input clock is 25 MHz. A 32.768 kHz crystal supplies the real-time clock
(RTC) inputs of the processor. The default boot mode for the processor is
external parallel flash boot. See
“Boot Mode Select Switch (SW1)” on
page 2-10 for information on how to change the default boot mode.
Programmable Flags
The processor has 50 general-purpose input/output (GPIO) signals spread
across four ports (
PF
,
PG
,
PH
, and
PJ
). The pins are multi-functional and
depend on the ADSP-BF526 processor setup. The following tables show
how the programmable flag pins are used on the EZ-Board.
•
PF
programmable flag pins in Table 2-1
•
PG
programmable flag pins in Table 2-2
•
PH
programmable flag pins in Table 2-3
•
PJ
programmable flag pins in Table 2-4
Table 2-1. PF Port Programmable Flag Connections
Processor Pin Other Processor Function EZ-Board Function
PF0 PPID0/DR0PRI/ND_D0A
Default:
PPID0
on
P3.18
via
RN1
.
Land grid array via
P7.A
.
PF1 PPID1/RFS0/ND_D1A
Default:
PPID1
on
P3.17
via
RN1
.
Land grid array via
P7.A2
.
PF2 PPID2/RSCLK0/ND_D2
Default:
PPID2
on
P3.20
via
RN1
.
Land grid array via
P7.A4
.
PF3 PPID3/DT0PRI/ND_D3A
Default:
PPID3
on
P3.19
via
RN1
.
Land grid array via
P7.A5
.