ADSP-BF526 EZ-Board Evaluation System Manual
1-25
Using The ADSP-BF526 EZ-Board
running at the VDDEXT voltage of 1.8V, requiring a voltage translator
(
U32
) to translate the 1.8V processor signals to the UART 3.3V line
transceiver.
The
UART1
interface is disconnected from the ADM1385 transceiver by
ensuring that no jumper is installed on
JP3
. The ADM1385 transceiver is
shut down by placing a jumper on
JP14
. The
UART1
interface is controlled
by the inverted
WAKEUP_OUT
signal,
WAKEUP_OUT
. To set up
WAKEUP_OUT
,
place a jumper on the
JP3
positions 1 and 2. A jumper on positions 1
and 2 of
JP3
disables the voltage translator, disconnecting the ADM1385
device from the
UART1
interface of the processor. This
JP3
setting does not
shut down the transceiver. For more information on power saving capabil-
ities of the EZ-Board, see
“UART Enable Jumper (JP3)” on page 2-20
“UART SD Jumper (JP14)” on page 2-23
.
SW14
allows the flow control signals to be looped back. See
for more information.
When using
UART1
, do not install jumper
JP2
.
JP2
is a UART loopback
jumper and should be installed only when running the POST program. If
signals
RTS
and
CTS
are needed for flow control, the
UART1RTS
port pin
PF10
can be configured as a general-purpose I/O (GPIO) pin for
RTS
. The
HWAIT
port pin
PG0
can be used for
CTS
by setting up the pin accordingly;
see
“UART Loopback Jumper (JP2)” on page 2-20
for more information.
UART0
and
UART1
are connected to the expansion interface II at connectors
P2
and
P4
.
For more information, see “Expansion Interface II Connectors
Example programs are included in the EZ-Board installation directory to
demonstrate UART and RS-232 operations.
On the processor,
UART1
shares pins with the PPI interface; conse-
quently, do not use
UART1
at the same time as the PPI interface. To
disable the UART line drive, ensure that
JP3
has no jumpers on.
Содержание ADSP-BF526 EZ-Board
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