Analog Devices ADSP-BF526 EZ-Board, Руководство пользователя

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Jumpers
2-20 ADSP-BF526 EZ-Board Evaluation System Manual
UART Loopback Jumper (JP2)
The
UART
loopback jumper (
JP2
) is used to place the
UART1
port of the pro-
cessor in a loopback condition. The jumper connects the
UART1_TX
line of
the processor to the
UART1_RX
signal of the processor. The jumper is
required when the POST program is run to test the serial port interface.
By default,
JP2
is uninstalled.
UART Enable Jumper (JP3)
The UART enable jumper (
JP3
) is a three-pin jumper that controls the
output enable (
OE
) of the
UART1
voltage translator. When
JP3
is unin-
stalled, the voltage translator outputs are tri-stated. When a jumper is
placed on positions 1 and 2 of
JP3
, the inverted copy of the
WAKEUP_OUT
signal (
WAKEUP_OUT
) controls the output enable of the voltage translator.
When the EZ-board boots, the processor enables the voltage translator;
when the processor is in hibernate, the translator outputs are tri-stated. A
jumper on positions 2 and 3 of
JP3
allows the translator to drive the out-
puts. See “Power Architecture” on page 1-30 for more information on
power saving capabilities of the ADSP-BF526 EZ-Board. By default,
JP3
is installed on positions 1 and 2.
LED Enable Jumper (JP5)
The LED enable jumper (
JP5
) enables the power saving feature of the
board through control of the voltage translator’s output enable pins.
When no jumper is installed on
JP5
, the voltage translator (
U3
), which
controls the GPIO LEDs, and the
OTP_FLAG
signals are tri-stated. Placing a
jumper on positions 1 and 2 of
JP5
allows the inverted
WAKEUP_OUT
signal
(
WAKEUP_OUT
) to control the output enable of the translator. When the
processor is not in hibernate, the translator is enabled; when the processor
is in hibernate, the translator outputs are tri-stated. Placing a jumper on
positions 2 and 3 of
JP5
enables the translator outputs. See “Power Archi-
tecture” on page 1-30 and “Power Saving Features” on page 1-35 for more