EVAL-ADP8860
Rev. 0 | Page 15 of 24
The VDDIO supply line determines the logic levels for nRST,
nINT, SDA, and SCL.
When shunted, Jumper J31 and Jumper J32 connect the Cypress
I
2
C interface to the daughterboard, which is the default setting
for PC-to-adapter board communication. J31 and J32 must be
removed if the I
2
C interface (master) is provided from the
target (J30) to avoid bus contention.
JP1 selects the Sink 7 usage mode. If JP1 is in the
LED
position,
Sink 7 is connected to the D15 LED and can be used as individ-
ual sink or as part of the backlight. If JP1 is in the
KEYPD BL
position, Sink 7 is connected to the keyboard light LED block.
For demonstration purposes the adapter board contains two
LED lighting sections: the display backlight and the keypad
backlight. The former can be configured, through jumper
selection, to drive up to seven LEDs with up to 30 mA per LED.
The second LED section contains up to 10 LEDs with a jumper-
programmable current range. For example, D2 has two jumpers
associated with it: J6 and J7. D2 is disabled by removing both
jumpers. If only J6 is installed, D2 has a 100 Ω limiting (ballast)
resistor. If only J7 is installed, D2 has a 50 Ω limiting resistor. If
both jumpers are installed, the limiting resistor is the parallel of
two resistors or 33.3 Ω. The lower is the limiting resistor; the
higher is the driving capability per LED. The same applies for
all the other LEDs used for the keypad backlight.
It is possible to measure the total LEDs current by removing the
J1 and J2 jumpers and inserting a current meter across one of
the jumpers. Each LED current can be measured by removing
the individual LED selection (that is, J5 for D5, Sink 1 LED)
and inserting an ammeter. The ADP8860 input current can be
measured by removing Jumper LK6 in the daughterboard
and inserting a current meter across the jumper.
An external target hardware can be connected to the adapter
and daughterboard using a J30 connector. The signals available
are indicated in Figure 30.
GROUND (GND)
PHOTOTRANSISTOR SUPPLY VOLTAGE (+VS)
GROUND (GND)
EXTERNAL PHOTOTRANSISTOR 2 (I_PHS2)
GROUND (GND)
EXTERNAL PHOTOTRANSISTOR 1 (I_PHS1)
GROUND (GND)
LOGIC VOLTAGE LEVEL (VDDIO)
RESET INPUT (nRST)
INTERRUPT OUTPUT (nINT)
I
2
C SERIAL CLOCK LINE (SCL)
I
2
C SERIAL DATA LINE (SDA)
BATTERY VOLTAGE SUPPLY (VBATT)
CHARGE-PUMP OUTPUT VOLTAGE (VOUT)
SINK 7 – LED7 ANODE
SINK 7 – LED7 CATHODE
SINK 6 – LED6 ANODE
SINK 6 – LED6 CATHODE
SINK 5 – LED5 ANODE
SINK 5 – LED5 CATHODE
SINK 4 – LED4 ANODE
SINK 4 – LED4 CATHODE
SINK 3 – LED3 ANODE
SINK 3 – LED3 CATHODE
SINK 2 – LED2 ANODE
SINK 2 – LED2 CATHODE
SINK 1 – LED1 ANODE
SINK 1 – LED1 CATHODE
28
26
24
22
20
18
16
14
12
10
8
6
4
2
27
25
23
21
19
17
15
13
11
9
7
5
3
1
J30
07988-
030
Figure 30. Target Connector J30
The target can either control the circuit in the adapter board or
be driven by the daughterboard, such as when the LEDs reside
on the target board. Also, I
2
C commands can be sent in either
direction. When the target provides the I
2
C interface, however,
the J31 and J32 jumpers must be removed.
