Analog Devices ADE9000, Техническое справочное руководство

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UG-1098 ADE9000 Technical Reference Manual
Rev. 0 | Page 4 of 86
Interfacing to Current and Voltage Sensors
Figure 4 and Figure 6 show the recommended circuits to
connect to current transformer sand Rogowski coil current
sensors. Figure 5 shows the interface circuit to measure the
mains voltage.
The antialiasing filter corner is chosen around 7 kHz to provide
sufficient attenuation of out of band signals near the modulator
clock frequency. The same RC filter corner is used on voltage
channels as well, to avoid phase errors between current and
voltage signals. Note that the Rogowski coil input network has a
second-order antialias filter to further reduce out of band noise
because the Rogowski sensor has a 1/f response.
1kΩ
Rb1
22nF
AGND
IxP
IxN
0.707Vrms max
CT
I
Rb2
1kΩ
22nF
AGND
15523-
004
Figure 4. Application Circuit with Current Transformer Current Sensor
1MΩ
1kΩ
22nF
AGND
VxP
VxN
0.240V rms
240V rms
1kΩ 22nF
NEUTRAL
PHASE
AGND
15523-
005
Figure 5. Application Circuit with Voltage Sensed Through Resistor Divider
1kΩ
IxP
IxN
0.3535V rms
22nF 22nF
100Ω
1kΩ
22nF 22nF
100Ω
15523-
006
Figure 6. Application Circuit with Rogowski Coil Current Sensor
INTERNAL RF IMMUNITY FILTER
Energy metering applications require the meter to be immune
to external radio frequency fields of 30 V/m, from 80 MHz up
to 10 GHz, according to IEC 61000-4-3. The
ADE9000 has
internal antialiasing filters to improve performance in this
testing because it is difficult to filter these signals externally.
The second-order, internal low-pass filter (LPF) has a corner
frequency of 10 MHz. Note that external antialias filters are
required to attenuate frequencies above 7 kHz, as shown in the
Interfacing to Current and Voltage Sensors section.
MODES OF OPERATION
Each ADC has two modes of operation: normal mode and
disabled mode.
In the normal mode of operation, ADCs are turned on and
sample continuously. The CHNL_DIS register can be used to
disable the ADCs individually.
There are 2 different power modes available in the
ADE9000
(see the Power Modes section). All ADCs are turned on in
PSM0 power mode. In PSM3 mode, all ADCs are disabled and
cannot be turned on.
Table 1. ADC Operation in PSMx Power Modes
PSMx Power Mode ADC Mode of Operation
PSM0 Normal (on)
PSM3 Disabled (always off)
OUTPUT DATA RATES AND FORMAT
When a conversion has been completed, the DREADY bit of the
STATUS0 register is set to 1. If the CF4_CFG[3:2] bits in the
CONFIG1 register are equal to 11, the CF4/EVENT/DREADY
pin corresponds to DREADY and pulses high to indicate when
seven new ADC results are ready.
In the
ADE9000 , the modulator sampling rate (MODCLK) is
fixed at 2.048 MHz (CLKIN/12 = 24.576/12). The output data
rate of the sinc filter is MODCLK/64, whereas the low-pass
filter/decimator stage yields an output rate 4 times slower than
the sinc filter output rate. Figure 7 shows the digital filtering
that takes the 2.048 MHz ADC samples and creates waveform
information at a decimated rate of 32 kHz or 8 kHz.
ANALOG
INPUT
Σ-Δ × 7
DIGITAL
MULTIBIT
SINC4
IIR LPF/
DECIMATOR
DIGITAL
WAVEFORM
WAVEFORM
BUFFER
(×7 CHANNELS)
2.048MHz
32kHz
8kHz
15523-
007
Figure 7. Datapath Following ADC Stage
The output data rates are summarized in Table 2.
Table 2. Output Data Rates
Parameter Output Data Rate
CLKIN Frequency 24.576 MHz
ADC Modulator Clock, MODCLK 2.048 MHz
SINC Output Data Rate, SINC_ODR 32 kHz
Low-Pass Filter Output Data Rate 8 kHz
3 dB Bandwidth 3.2 kHz