UG-1098
ADE9000 Technical Reference Manual
Rev. 0 | Page 24 of 86
The CVARSIGN, CWSIGN, BVARSIGN, BWSIGN, AVARSIGN,
and AWSIGN bits in the PHSIGN register indicate whether the
total or fundamental VAR and WATT selected in the
PWR_SIGN_SEL[1:0] bits are positive or negative.
The power signs are updated at the same time as the
xWATT_ACC, xFWATT_ACC, xVAR_ACC, and xFVAR_ACC
registers and correspond to the sign of these registers. Note that
the power registers and signs are updated after the number of
f
DSP
= 8 ksps samples configured in the PWR_TIME register
have elapsed, from 250 µs to 1.024 sec. The power sign change
indication in the REVxPx bits are updated at the same time; see
the Power Accumulation Details section for more information.
The
allows the user to accumulate total watt and VAR
powers into separate positive and negative registers:
PWATT_ACC and NWATT_ACC, PVAR_ACC and
NVAR_ACC. This is done by evaluating the AWATT, low-pass
filtered active power every 8 ksps. If the AWATT is positive, it is
added to the PWATT_ACC accumulation. If the AWATT is
negative, the absolute value is added to the NWATT_ACC
accumulation. A new accumulation from zero begins when the
power update interval set in PWR_TIMER has elapsed. The
positive and negative total watt and total VAR from all three
phases are added into the positive/negative watt and VAR
accumulations.
AWATT
INTERNAL POWER
ACCUMUL ATOR
AWATT, LOW PASS
FILTERED
ACTIVE POWER
POSITIVE
ACTIVE POWER,
PWATT_ACC
PHASE A ACTIVE POWER
SIGN INDICATION:
AWSIGN, IN PHSIGN
POWER UP DATE INTERVAL
SET IN PWR_TIME
ACCUMULATED
ACTIVE POWER,
AWATT_ACC
NEGATIVE
ACTIVE POWER,
NWATT_ACC
PHASE A ACTIVE POWER
SIGN CHANGE INDICATION:
REVAPA, IN STATUS0
CLEARED AFTER USER WRITES STATUS0
REGISTER WITH REVAPA BIT SET,
15523-
026
Figure 26. Power Accumulation and Power Sign
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
The
offers zero-crossing detection on the VA, VB, VC,
IA, IB, and IC input signals. The neutral current channel, IN,
does not contain a zero-crossing detection circuit. The zero-
crossing circuit is used as the time base for resampling, line
period, angle measurements, and energy accumulation using
line cycle accumulation mode. The xV_PCF and xI_PCF are the
voltage and current channel waveforms processed by the DSP,
and which can be stored into the waveform buffer at a 8 ksps data
rate (see the Waveform Buffer section for more information).
The ZX_SRC_SEL bit in the CONFIG0 register sets whether
data going into the zero-crossing detection circuit comes before
or after the high-pass filter, integrator, and phase compensation.
By default, the data after phase compensation is used. Note that
the high-pass filter has 500 ms settling time with a step change
in the input; therefore, for a fast response, it is recommended to
set ZX_SRC_SEL to look for a zero-crossing before the high-
pass filter. If a high-pass filter is disabled with the HPFDIS bit in
the CONFIG0 register equal to 1, or if the ZX_SRC_SEL bit in
the CONFIG0 register is equal to 1, note that a dc offset on the
input may cause the time between negative to positive and
positive to negative zero-crossings and positive to negative to
negative to positive zero-crossings to change, indicating that the
ZX detection does not have a 50% duty cycle.
The current and voltage signals are low-pass filtered to remove
harmonics. The low-pass filter, LPF1, has a corner of 82 Hz and
the equation is as follows:
1
4
)
4
1
(
1
2
)
(
−
−
−
−
=
z
z
H
The low-pass filter settling time is 71 samples, 71/8 ksps, which
equals 8.875 ms.
Figure 27 shows the delay between the detected zero-crossing
signal and the input. Note that there is a 4.3 ms delay between
the input signal zero-crossing and the ZX zero-crossing
indication, with a 50Hz input signal. Zero-crossings are
generated on both negative to positive and positive to negative
transitions.
IA, IB, IC,
OR VA, VB, VC
4.3ms AT 50Hz
1
0.86
0V
ZX
ZX
ZX
ZX
LPF1 OUTPUT
15523-
027
Figure 27. Zero-Crossing Detection on Voltage and Current Channels
To provide protection from noise, the voltage channel zero-
crossing events (ZXVA, ZXVB, and ZXVC) are not generated if
the absolute value of the LPF1 output voltage is smaller than the
threshold, ZXTHRSH. The current channel ZX detection outputs
(ZXIA, ZXIB, and ZXIC) are active for all input signals levels.
