ADE9000 Technical Reference Manual
UG-1098
Rev. 0 | Page 21 of 86
For example, with the MTEN bit in the CONFIG0 register equal
to zero, for single-point gain compensation and AIGAIN,
AVGAIN, APGAIN, and AWATTOS all equal to zero, the
Phase A total active energy has a digital gain of 1. Then, the
Phase A total active energy accumulated in the user accessible
accumulator overflows in 106.4 sec with the nominal full-scale
AWATT value of 20,694,066.
sec
3
.
106
8000
20,694,066
2
(sec)
44
=
×
=
Time
r
Accumulato
Energy
Internal
Maximum
Accessing the User Energy Registers
Each 45-bit user accessible signed energy accumulator is
divided into two registers: a register containing the 32 most
significant bits, xHR_HI, and a register containing the 13 least
significant bits, xHR_LO, as shown in Figure 24.
f
DSP
INTERNAL ENERGY ACCUMULATOR
+
31
0
AWATTHR_HI
0
12
AWATTHR_LO
31
15523-
024
Figure 24. Internal Energy Register to AWATTHR_HI and AWATTHR_LO
The expected user energy accumulation can be calculated
according to this formula based on the average AWATT value.
USER_ENERGY_ACCUMULATION
=
AWATT
× (
EGY_TIME
+ 1)
Then, AWATTHR_HI contains the 32 most significant bits,
which can be calculated by rounding the following equation
down to the nearest whole number:
AWATTHR_HI
= ROUNDDOWN(
USER_ENERGY_ACCUMULATION
× 2
−13
)
The 13 LSBs of USER_ENERGY_ACCUMULATION are stored
in the AWATTHR_LO register.
Read User Energy Register with Reset
If the RD_RST_EN bit is set in the EP_CFG register, its contents
are reset when a user accessible energy register is read.
For example, if AWATTHR_HI is read, the AWATTHR_HI register
value goes to zero. The AWATTHR_LO register contents are
not modified.
User Energy Register Use Models
There are three main use models for energy accumulation:
•
Read energy register with reset
•
Accumulate energy over a defined number of line cycles
•
Accumulate energy over a defined number of samples
To read energy register with reset, use the following settings:
•
Configuration register settings:
•
EP_CFG register, EGY_LD_ACCUM bit = 0.
•
EP_CFG register, EGY_TMR_MODE bit = 0.
•
EP_CFG register, RD_RST_EN bit = 1.
•
EP_CFG register, EGY_PWR_EN bit = 1.
•
EGY_TIME register = 1.
•
Output: read just the xHR_HI register, which has enough
resolution for most applications. The xHR_LO register is
maintained and accumulated and does not need to be read
by the user.
•
Maximum time before reading xHR_HI to prevent
overflow with full-scale inputs: 106 sec.
To accumulate energy over a defined number of half line cycles,
use the following settings:
•
Configuration register settings:
•
EP_CFG register, EGY_LD_ACCUM bit = 1.
•
EP_CFG register, EGY_TMR_MODE bit = 1.
•
EP_CFG register, RD_RST_EN bit = 0.
•
EP_CFG register, EGY_PWR_EN bit = 1.
•
EGY_TIME register = desired number of half line
cycles.
•
Output:
•
The xHR_HI register has enough resolution for most
applications.
•
To maintain perfect synchronization with CF pulse
output, the xHR_LO register must be read as well,
because it is cleared at every EGYRDY cycle.
•
Maximum time before reading xHR_HI to prevent
overflow with full-scale inputs: 13.3 sec.
To accumulate energy over a defined number of samples, use
the following settings:
•
Configuration register settings:
•
EP_CFG register, EGY_LD_ACCUM bit = 1
•
EP_CFG register, EGY_TMR_MODE bit = 0
•
EP_CFG register, RD_RST_EN bit = 0
•
EP_CFG register, EGY_PWR_EN bit = 1
•
EGY_TIME register = desired number of samples
•
Output:
•
The xHR_HI register has enough resolution for most
applications.
•
To maintain perfect synchronization with CF pulse
output, the xHR_LO register must be read as well,
because it is cleared at every EGYRDY cycle.
•
Maximum time before reading xHR_HI to prevent
overflow with full-scale inputs: 13.3 sec.
